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Webinar Report: Power-Aware Mixed-Signal Verification

Comments(0)Filed under: Industry Insights, low power, Virtuoso, CPF, Analog, Mixed-Signal, mixed signal, low-power, AMS Designer, AMS, Power, SPICE, SystemVerilog, webinar, assertions, analog/mixed-signal, SVA, analog assertions, PSL, Property Specification language, parasitic flow, Verilog, Bhattacharya, mixed-signal assertions, mixed signal simulation

Most of the discussion about low-power design techniques has focused on digital circuits. However, nearly all systems-on-chip (SoCs) are mixed-signal, and the way in which analog and digital circuitry interact has a huge impact on overall power consumption. Thus, low power (or "power aware") verification must encompass both analog and digital - but how?

A recently archived Cadence webinar has some answers. Titled "Advanced Technology to Verify Complex Mixed-Signal Designs," the webinar was presented by Prabal Bhattacharya, simulation architect at Cadence. The webinar covered advanced mixed-signal verification topics including parasitic simulation, assertions, and low power. A recent blog post summarized the first part of this webinar; this post focuses on the last portion, which described power-aware mixed-signal verification using the Common Power Format (CPF).

Bhattacharya started this portion of the webinar by reviewing some basic concepts and showing how they apply to mixed-signal circuits. These concepts included power domains, state loss, isolation, power shutoff, and multiple supply voltage (MSV). In the latter case, he noted, supply voltage may vary from 1.2V to 1.8V or higher based on whether various conditions are true or false. This means the operating voltage of the block is dynamically changing during simulation.

"I think the primary challenge is that you have to do the conversion of the circuit's signal and low-power information," Bhattacharya said. "It is not enough to take an analog signal and bring it to the digital level, or a digital signal to the analog level. You have to think of the low power intent of that analog or digital block."

So how to do that? Earlier in the webinar, Bhattacharya introduced the concept of logic-to-electrical and electrical-to-logic "connect modules" that are automatically inserted by the simulator. In discussing low power, he introduced "power aware" connect modules. Shown below is a power-aware connect module (CM) that does a logic-to-electrical conversion using the power intent information in a CPF file. In this example a digital driver in a power domain (PD1) is driving an analog block in another power domain (PD2). The connect module takes power into account as it does the value conversion for the analog block.

Bhattacharya also talked about dynamic macro-model verification. A macro-model is typically a black box with no information about what's inside it. Thus, a chip-level verification engineer will focus on its boundary. However, he or she may need to verify that the analog value on an output port, as specified by CPF, matches the value that SPICE sees from the inside of the port. Bhattacharya showed how engineers can write a Property Specification Language (PSL) assertion to verify that the output voltage is within a desired range of tolerance.

"The main thing we want to emphasize is that the connect modules need to be power aware," Bhattacharya concluded. "You should be able to keep reusing your CPF specification even though some blocks are analog. You can do dynamic verification or assertion-based verification at the boundary to verify your low power intent."

You can access the archived webinar here.  It's available free to members of the Cadence Community - quick and easy signup if you're not.

Richard Goering



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