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Webinar Report – New Approaches to Mixed-Signal Verification and Assertions

Comments(0)Filed under: Industry Insights, Virtuoso, Analog, Mixed-Signal, mixed signal, AMS Designer, AMS, SPICE, SystemVerilog, webinar, assertions, analog/mixed-signal, SVA, analog assertions, PSL, Property Specification language, parasitic flow, Verilog, Bhattacharya, mixed-signal assertions, mixed signal simulation

Nearly all systems-on-chip (SoCs) are mixed-signal, and as complexity grows, new verification techniques are needed. No longer is it sufficient to use traditional analog and digital simulation in isolation - instead, information must flow freely between analog and digital domains to allow a true mixed-signal simulation. A recently archived Cadence webinar showed how this can be done using a mixed-signal parasitic flow, assertions, and low-power verification.

The webinar, titled "Advanced Technology to Verify Complex Mixed-Signal Designs," was presented by Prabal Bhattacharya, simulation architect at Cadence. It was so full of information that I'll save an overview of power-aware mixed-signal simulation for a follow-up blog post. (Separately, Bhattacharya co-authored a detailed article about mixed-signal assertions for EE Times last year).

Introducing the webinar, Bhattacharya noted that traditional verification approaches based on SPICE and Verilog resulted in "limited channels of communication" between analog and digital teams.  "Mixed signal has evolved to the point where you have continuous time domain and discrete time domain objects that interact with and influence each other," he said. He pointed to a simple model in which a voltage equation is driven by a variable that is set by a logic event. A true mixed-signal simulator must "play across" analog and digital domains, he said.

Bhattacharya showed the mixed-signal functional verification "landscape" shown below. On the left side, in the Cadence Virtuoso custom/analog environment, users design schematics, write analog behavioral models and wreal models, and create analog-centric testbenches. On the right side, users of the Cadence Incisive verification platform use methodologies such as metric-driven verification (MDV) and the Universal Verification Methodology (UVM) to provide chip-level verification. "You want to reuse all the things you've done in your Virtuoso environment and hand these off to Incisive by making minimal changes," he noted.

Next Bhattacharya discussed a mixed-signal parasitic flow.  Following a top-level simulation in Virtuoso AMS Designer, the analog designers create blocks with schematics, run layout and extraction, and generate Standard Parasitic Exchange Format (SDEF) and/or Detailed Standard Parasitic Format (DSPF) files. Digital block creation, on the other hand, uses RTL coding and generates Standard Delay Format (SDF) files. Bhattacharya showed how analog and digital domains come together through logic-to-electrical and electrical-to-logic "connect modules" that are automatically inserted by the simulator. Then AMS Designer can run a mixed-signal parasitic simulation.

Using Analog/Mixed-Signal Assertions

Assertion-based verification is very familiar in the digital world, but not among analog designers, Bhattacharya said. But wait - analog designers may not use the word "assertion," but they do some things that are similar. These include HSPICE .measure statements, Spectre assert device statements, UltraSim device checks, and behavioral monitoring code in Verilog-AMS. These are all fine at the pure analog block level, but they don't convey meaningful information to digital verification teams.

What's better, Bhattacharya said, is a standard language such as Property Specification Language (PSL) that can be used in both the analog and digital domains. While PSL has primarily been applied to digital logic, he showed how it can be extended to cover mixed-signal expressions with voltage and current. For example, you could write an assertion that says that at the next clock cycle, voltage must be positive at the positive edge of the clock. "When I ship a block to the digital integrator, there is a person there who also uses PSL and can see what I was doing in my pure analog world," Bhattacharya said.

What about System Verilog assertions? There is currently no SystemVerilog-AMS specification, but you can bring real number values into SystemVerilog assertions, Bhattacharya noted. A DAC output could go through an electrical-to-real conversion and come into a SystemVerilog testbench as a real number. Further, an "analog value fetch" capability can be used with Verilog, SystemVerilog or VHDL, among other languages, to bring in analog quantities including voltage, current, power, and device and netlist parameters as real number values.

Bhattacharya concluded this portion of the webinar by showing an assertion browser and comparing it to a waveform display. "You be the judge in whether you want to do this [assertions] or go back to eyeballing waveforms," he said.

You can access the archived webinar here. It's available free to members of the Cadence Community -- quick and easy signup if you're not.

Richard Goering


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