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Top Ten Cadence Community Blog Posts of 2011

Comments(0)Filed under: Industry Insights, Functional Verification, Allegro, Incisive Formal Verifier, UVM, SKILL, SystemVerilog, 3D IC, 3D-IC, e language, wide i/o, PDN, OrCAD Capture Marketplace, ccopt, Azuro, TLM 2.0, SKILL++, Cadence Community, Cadence blogs, top ten blog posts, Rubik's cube, Lego robot

Over  430 Cadence Community blog posts appeared in 2011, in categories including Industry Insights, Functional Verification, PCB Design, System Design & Verification, Custom IC, Digital Implementation, RF, Mixed Signal, and Low Power. By looking at the most widely-read posts, we can get a picture of what topics most excited readers in 2011. Here's a listing, in order, of the ten most widely read blog posts of 2011 (not including blogs posted in prior years).

User View: Is e or SystemVerilog Best for Constrained-Random Verification?

It's not a surprise that this Industry Insights post was our most-read 2011 blog post - the e language has a devoted following and many users are passionate about it. In this post Geoffrey Faurie, a member of the Functional Verification Group at STMicroelectronics, discussed the pros and cons of e compared to SystemVerilog. The post attracted numerous comments both on the blog posting itself and in several LinkedIn groups.

Wide I/O Memory and 3D ICs - A New Dimension for Mobile Devices

3D-ICs were a hot topic in 2011, and wide I/O memory, a specification under development by JEDEC, will be a major driver of this new technology. This Industry Insights post explains why the March 28 Cadence announcement of the first wide I/O memory controller IP will help spur the coming era of 3D integration.

TLM 2.0, UVM 1.0 and Functional Verification

In this Functional Verification blog post, Sharon Rosenberg provides a lengthy update on the Universal Verification Methodology (UVM) and Transaction Level Modeling (TLM) standards from an Accellera tutorial at the DVCon conference in February. Rosenberg is co-author of the Cadence-published Practical Guide to Adopting the Universal Verification Methodology.

Allegro 16.5 Powers up Allegro PCB PDN Analysis

Much of the low power discussion has focused on the chip level, but power is a big concern for packages and boards as well. The Allegro 16.5 power delivery network (PDN) feature provides a unique PCB design and analysis capability. This PCB Design blog post by Team Allegro explains why.

OrCAD Capture Marketplace - An Interactive, Application-Driven Approach to EDA

Representing a new way of providing EDA technology, the OrCAD Capture Marketplace is a web-based capability within the OrCAD Capture environment that provides an on-line store with free and paid plug-in tools, or "apps." This Industry Insights blog post introduces it and shows what the Marketplace includes.

The Tale of the Silicon Re-Spin and the Bug That Got Away

Readers enjoy real-life engineering stories, and this Functional Verification blog by Tom Anderson provides one. Unfortunately this post does not have a happy ending; it's the tale of the bug that got away and required a silicon re-spin to fix. It involves a FIFO error that could have been caught with a tool that does clock-domain crossing (CDC) checks. Such tools are available today, but not at the time of this story.

SKILL for the Skilled: What is SKILL++?

The Cadence SKILL language is a key value-add for users of the Virtuoso custom/analog and Allegro PCB platforms, and SKILL expert Jim Newton has written a number of informative "SKILL for the Skilled" posts for the Custom IC blog. This post introduces SKILL++, a subset of the language, and shows how to implement a design hierarchy traversal engine in SKILL++.

Why Cadence Bought Azuro - A Closer Look

Cadence announced July 12 its acquisition of Azuro, a provider of "clock concurrent optimization technology" (ccopt). This Industry Insights post shows how Azuro technology goes far beyond clock tree synthesis to provide a new IC physical implementation approach that offers compelling power, performance, and area advantages.

Video Easter Egg: Incisive Formal Verifier and SVA driving a Rubik's Cube robot

Team Verify's Apurva Kalia, Manu Chopra, and Suman Ray of the Incisive R&D team created a Rubik's Cube solving Lego robot.  However, unlike other such robots, the brain of this one is actually a single SystemVeriliog assertion. This entertaining Functional Verification video blog shows how it works.

User View: Where e Outshines SystemVerilog For Functional Verification

Here's another e and SystemVerilog perspective, this time from Michael Blech, a verification manager at PMC-Sierra's Fiber to the Home (FTTH) division. A read of this Industry Insights blog post shows why e will be around for a long time to come.

Thanks for reading Cadence Community blogs in 2011! I'm looking forward to blogging in 2012.

Richard Goering


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