Two prominent EDA industry standards organizations -- Accellera and the Open SystemC Initiative (OSCI) - announced today (Dec. 5) the completion of their merger under the name "Accellera Systems Initiative." The stage is now set for a unified EDA standards effort that cuts across multiple levels of abstraction, from the SystemC language developed by OSCI to the Verilog, SystemVerilog and VHDL hardware description languages for which Accellera is best known.
The pending merger was announced in June 2011 as a way of uniting front-end IC design standards activities at the systems, software, and RTL levels. It was presented from the start as a merger of equals rather than one organization folding into another. OSCI's five working groups have joined Accellera's seven working groups as equal partners. Shisphal Rawat, Accellera chair before the merger, is the current chair of the Accellera Systems Initiative.
The creation of the Accellera Systems Initiative "creates a single home for front-end EDA and IP standards," said Stan Krolikoski, Accellera Systems Initiative secretary and group director of standards at Cadence. "This will facilitate the exploiting of synergies between standards such as SystemC, UVM and IP-XACT, just to name three, and will also create an infrastructure under which synergistic standards efforts can be done in tight harmony from the beginning."
Synergies and Opportunities
What are some of the possible "synergies" that may arise from the combination of Accellera and OSCI into one organization? The following illustration shows opportunities in three areas:
Synergies and future opportunities. Source: Accellera Systems Initiative
- System-Level IP Integration - In 2010 the SPIRIT Consortium, developer of the IP-XACT metadata standard for IP integration, merged into Accellera. Consequently, Accellera is aligning IP-XACT register definitions with the Universal Verification Methodology (UVM). Now, Krolikoski said, there's a possibility of fully bringing SystemC descriptions into the information captured by IP-XACT.
- System-Level Verification - UVM has already implemented the OSCI TLM-2.0 (transaction-level modeling) standard. Presently UVM has been defined for SystemVerilog only, but there has also been some user interest in a UVM SystemC capability, as reflected in a "town hall" meeting at the DVCon conference in February. The OSCI Configuration, Control and Inspection (CCI) modeling specification could be a powerful adjunct to a UVM SystemC capability. Finally, the upcoming Unified Coverage Interoperability Standard (UCIS) could be enhanced to work with SystemC.
- Mixed-Signal Design and Verification - Verilog-AMS (analog/mixed-signal) and SystemC-AMS standardization efforts have so far been disconnected, but now that both are under one roof, mapping between SystemC-AMS and Verilog-AMS may become possible.
On the organizational level, Krolikoski noted, the Accellera Systems Initiative retains a strong technical chair (Karen Pieper, Tabula), which is not a position that OSCI had. The Accellera Systems Initiative has a Marketing Committee, a capability that OSCI had but Accellera did not. It is chaired by Thomas Li of Springsoft.
The following seven working groups came from Accellera:
- Interface Technical Committee - SCE-MI standard for co-emulation and transaction-based acceleration
- IP-XACT Working Group -- Metadata standard for IP integration
- IP Tagging Technical Committee - Tracking IP throughout development process
- Open Verification Library Technical Committee - OVL assertion library
- Unified Coverage Interoperability Standard (UCIS) - Verification coverage interoperability
- Verification Intellectual Property Technical Committee - Universal Verification Methodology (UVM) standard
- Verilog-AMS Technical Committee - Analog/mixed-signal extensions to Verilog
The following working groups came from OSCI:
- AMS- Analog/mixed-signal extensions to SystemC
- Configuration, Control and Inspection - Standards for exchange of information between SystemC models and tools
- Language - SystemC language standard
- Synthesis - Synthesizable subset of SystemC
- Transaction Level Modeling (TLM) - OSCI TLM 1.0 and 2.0 modeling standards
Both OSCI and Accellera targeted eventual IEEE standardization. IEEE working groups supported by the Accellera Systems Initiative include IEEE 1076 (VHDL), IEEE 1800 (SystemVerilog), IEEE 1801 (Unified Power Format), and IEEE 1666 (SystemC).
Further information will be available at the Accellera Systems Initiative web site (site temporarily unavailable until Dec. 6).