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Archived Webinar: Bringing SystemC and C/C++ Models into UVM

Comments(0)Filed under: Industry Insights, SystemC, TLM, Accellera, verification, Functional Verification, Incisive, Verification IP, VIP, SystemVerilog, webinar, UVM 1.0, Sherer, multiple languages, UVM_ML, UVM world, C/C++, SimVision, Huynh

If you use or plan to use C language models for verification - be they SystemC, C, or C++ -- you will probably want to connect them to a SystemVerilog verification environment. How can this be done? A newly archived Cadence webinar has the answer - use the multi-language support capability that Cadence developed for the Universal Verification Methodology (UVM), available as an open-source contribution at http://www.uvmworld.org/.

The webinar is titled "Oceans of Expertise Connecting the UVM to Sea (C/C++/SC)." Presenters are Adam Sherer, product marketing director at Cadence, and Phu Huynh, verification architect at Cadence. Sherer is also secretary of the Accellera committee that's working on UVM.

First, a bit of background. UVM 1.0 and 1.1, as standardized by Accellera, describe a verification methodology for SystemVerilog. The Cadence UVM-ML (multi-language) donation extends UVM to the e language and SystemC (although this webinar was focused on SystemC). Sherer noted in the webinar that Accellera is not expected to consider a multi-language version of UVM until after the release of UVM 1.2 next year. So for now, what was discussed in the webinar is freely available but is not yet an Accellera standard.

Why Multiple Languages?

A system-on-chip (SoC) verification project today can be like the proverbial Tower of Babel. As shown at right, Verification IP (VIP) and universal verification components (UVCs) may exist in different languages, including SystemVerilog, e, SystemC, or C/C++. If you want to put all this together into a UVM style testbench, you need something that makes it possible to coordinate and synchronize those verification components.

Sherer took a quick poll at the start of the webinar and found that most attendees use the SystemVerilog Direct Programming Interface (DPI) to connect SystemC or C/C++ models to UVM. "DPI is good, but one of the problems is that you don't have any standard API to connect the SystemC or C++ components to UVM," Huynh said. "That is what we are trying to address with the multi-language UVM solution."

Huynh noted that there are some issues to be taken care of when integrating components from different language domains. These include synchronizing the execution and phases of components, communicating between the components, and providing some unified common utilities. To allow synchronization and communication, the UVM-ML capability uses the Open SystemC Initiative (OSCI) transaction-level modeling (TLM) standard. (Note: examples in this webinar were given in TLM 1.0, but Cadence is also developing a TLM 2.0 capability for UVM-ML).

Key TLM Terminology

In the webinar, Huynh reviewed some of the basic concepts behind the TLM interface. Important terms include "port" and "export" and "initiator" and "target." For example, when a consumer pulls items from a producer using a TLM "get" function, the consumer is the initiator (see below). Conversely, when a producer pushes items to a consumer using a "put" function, the producer is the initiator. The "port" is the component that initiates the TLM operation, and the "export" is the component that implements the TLM operation. (A questioner noted, and Huynh agreed, that this SystemC terminology is backwards from what some people would expect).

 

To make a connection, Huynh explained, the user "wraps" the C language model with a SystemC wrapper that provides the required TLM port and export. The synchronization of phases (such as end_of_elaboration and end_of_simulation) is handled automatically by the Cadence UVM-ML extensions. As Huynh noted several times, there are just three basic steps to connecting SystemC components into UVM:

  • Make sure the transaction exists on both sides (ensure you can transfer transactions across language boundaries, with the same class name and order and type of class variables)
  • Register the TLM port/export of the components using the UVM-ML library registration method
  • Make the connection via TLM port and export, using methodology defined in UVM-ML

Huynh showed an example in which a SystemC reference model for a packet router was brought into a UVM verification environment and integrated into a UVM testbench. He also showed multi-language debugging using the Cadence Incisive SimVision interface. You can see this example for yourself on the UVM World site.

In summary, I think the webinar did represent "oceans of expertise" that you can tap into in order to develop a multi-language capability with UVM. But Cadence has already handled a lot of the depth with its UVM-ML contribution. To access the archived webinar, click here.

Richard Goering

 

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