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Webinar: How to Stop “Insidious” Bugs at the HW/SW Interface

Comments(0)Filed under: Industry Insights, automation, Incisive, UVM, registers, Murray, Duolog, register package, Socrates, hardware/software integration, insidious bug, Sid, specifications, Sherer, hardware/software interface, Bitwise, HW/SW interface

Meet Sid, the "insidious" hardware/software interface bug. He was the star, so to speak, of a recent Duolog Technologies-Cadence webinar now archived at the Duolog web site. The webinar shows how hardware/software interface bugs arise, how they can be uncovered with help from the Universal Verification Methodology (UVM) register package, and how an automated register management tool can make life even more difficult for Sid and his kind.

The webinar is titled "Automating UVM to Tackle Insidious HW/SW Bugs." Presenters are David Murray, Duolog CTO, and Adam Sherer, director of verification solutions at Cadence. Murray kicked off the webinar by noting the importance of concurrent hardware/software development. "We want to make sure that software can be developed earlier, we want to make sure software is looking at a very accurate model of the hardware, and that we can also allow continuous hardware/software integration on an hourly or daily basis," he said.

HW/SW Interface: It's Harder Than it Looks

Murray showed a simplified "programmers view" of the hardware/software interface, took a deeper look at the IP level, and then showed a diagram of a hardware register that didn't look at all simple. "When you go into a register they are very complex," he said. Indeed, there are many attributes associated with registers - name, register reset, offset, access type, bitfield access, and bitfield reset, to name a few.  A bitfield can have its own reset value and access types. It all adds up to a lot of information that needs to be managed, and that's where Sid can easily enter the picture.

"This [register] structure needs to be understood and implemented in the right way," Murray said. "Someone writes a spec, but the spec can be interpreted and implemented in a variety of different ways. There's a lot of duplication of information, a lot of manual processes, and communication between teams starts falling down."

It's very easy to make a small, subtle error that can cause weeks of effort in the lab. That's the nature of an "insidious" bug - "proceeding in a gradual, subtle way but with harmful effects," as Murray said. Dynamics that lead to insidious bugs include incorrect, unclear, or incomplete specifications; errors in translation to an implementation format; and mismatches (lack of synchronization) between different implementations.

UVM to the Rescue

The Accellera UVM 1.0 standard includes a register package, which provides an infrastructure that can verify the hardware/software interface. It comes with pre-packaged test cases, making it very easy to do hardware/software integration testing, Murray said. He walked through a detailed demo that showed UVM working in concert with the Cadence Incisive Enterprise Simulator to track down a bug in which someone changed a reset value without changing the spec.

"UVM caught the bug," Murray noted, "however, the spec is open to interpretation. There is a possibility we will get symmetrical errors. That means that people designing IP and people verifying IP can make the same mistakes, and it will not appear as an error -- you will get a false positive."

Automation is the solution, Murray said, and he discussed the Socrates Bitwise tool from Duolog, which provides a formal, executable specification of the hardware/software interface.  "When you capture something with a register management tool like Bitwise, the quality of the specification is going to be much better, the interpretation is going to be automatic, and there's a correct by construction flow all the way down to implementation." In a follow-up demo, Murray showed how UVM in concert with Incisive and Bitwise was able to find an "insidious bug that was in the background the whole time."

Sherer said that Cadence provides a register generation capability for UVM, but Bitwise goes one step further by providing not just generation but static analysis to make sure the specification is captured correctly. "Customers are working with register environments with hundreds of thousands of register descriptions, far beyond the ability of a human to manage," he said. "I encourage our customers to look at automation for this specification and for UVM, and Duolog is a great choice."

The webinar is available here. Registration is required.

Richard Goering

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Sid graphic courtesy of Duolog Technologies




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