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ARM TechCon Address: High Stakes at Low Process Nodes

Comments(0)Filed under: Industry Insights, ARM, low power, Si2, CPF, Chi-Ping Hsu, broadcom, 32nm, Silicon Realization, GlobalFoundries, collaboration, DRC+, 28nm, TSMC, ARM Techcon, Techcon, 20nm, Cadence, clock concurrent optimization, Hsu, Ambarella, Cortex0-A15, FinFET

The complexity of advanced-node IC designs is skyrocketing, and the demands on EDA tool development seem overwhelming - but innovation and deep collaboration will break through the challenges, according to Chi-Ping Hsu, senior vice president for R&D at the Silicon Realization group at Cadence. In an Industry Address at the ARM TechCon conference Oct. 25, Hsu tackled some of the toughest challenges in IC design and showed how collaboration is providing solutions.

The demand for advanced process nodes is strong, Hsu noted. He pointed to the tremendous growth in the number of connected devices, the explosion of software "apps," and the proliferation of mobile devices. Customers in the consumer, computer and communications markets are moving ahead with 32/28nm and 22/20nm process nodes, Hsu said.

But these advanced nodes come with a cost. Fab investment in the 32/28nm node was around $3 billion, process R&D was around $1.2B, and a single system-on-chip (SoC) design may cost $50-$90 million. These costs will nearly double at 20nm. What nobody seems to talk about, Hsu noted, is the aggregate EDA tool development costs. He estimated these costs at $400-$500 million at 32/28nm and $800 million - $1.2B at 22/20nm.

Horizontal to Vertical

Hsu noted that the semiconductor supply chain has gone through a "horizontal segmentation" in which pure-play foundries have spun off, commercial EDA companies have emerged, and IP companies including ARM have arisen. Now that design has gotten really tough, what is needed is "vertical collaboration" that cuts across these horizontal segments. To illustrate this point Hsu showed a short video in which executives from Cadence, Broadcom, ARM and TSMC talked about collaboration between their respective companies.

One industry challenge that has responded to collaboration is low-power design. Five years ago, Hsu said, only a handful of customers with internal tool capabilities were doing advanced low-power designs. Even then, "it was all done at the gate level or transistor level as an afterthought," and many of the chips didn't work. Cadence developed a new methodology and worked with some 40 partners to refine it. The specification was later donated to the Silicon Integration Initiative (Si2). This was a reference to the Common Power Format (CPF), and you can read the latest update, from the Si2 Conference last week, here.

"Instead of a half-dozen high end customers, we enabled fabless semiconductor companies to have the same kind of [low power] capability," Hsu said. He went on to note that there are still low power challenges to solve, including analog/RF design. Hsu noted that Cadence has extended its low power methodology into the analog/custom arena, and he also spoke about the power analysis capability available with Cadence Palladium emulators.

An "exciting" new development that can help save power, Hsu said, is the clock concurrent optimization technology that Cadence acquired from Azuro (see my previous blog post for background). This technology combines clock tree synthesis and logic optimization into a single step, and it has been shown to increase performance and (not or!) decrease power and decrease area in SoCs with embedded ARM processors. With this technology, Hsu said, "we are breaking the traditional way of doing optimization and setting up a new paradigm."

20nm Challenges

Hsu cited a number of challenges on the road to 20nm, including 400 new design rules, layout-dependent effects, and double patterning. He showed how double patterning, which uses extra masks to make conventional lithography possible at 20nm, has impacts throughout the full-custom and digital implementation flows. He also showed some solutions that Cadence has developed to assist the colorized layout decomposition that double patterning requires.

At 20nm and below, FinFET devices have some area, frequency, and power advantages, Hsu said. He noted that Cadence is working with several foundries on this technology and already has a working FinFET Berkeley SPICE model.

Hsu noted that Cadence, TSMC, and ARM worked together to produce the first 20nm ARM Cortex-A15 tapeout, as announced last week. He also noted that Cadence and Samsung have worked together on a 20nm test chip tapeout. Finally, he pointed to an announcement today (Oct. 25) about a 32nm SoC designed at Ambarella in cooperation with Samsung and Cadence. The chip goes into a 16 megapixel HD digital camera that can take 30 pictures in one second (see Steve Leibson's blog post for more information). The chip achieves a 95% power savings during shutoff mode and a 60% power savings in sleep mode.

The Ambarella story is "just a tremendous collaboration," Hsu said. "If we hadn't done the collaboration work in this vertical way, a startup like this could never have done this kind of design."

Hsu also pointed to Cadence work with GLOBALFOUNDRIES on the DRC+ pattern-matching technology; work with lithography verification with TSMC; and finally, Cadence support for 2.5D and 3D-IC designs. "Vertical collaboration with all our partners is important," he concluded. "We are committed to helping our customers be successful."

ARM TechCon runs Oct. 25-27 in Santa Clara, Calif. Cadence presentations, activities and papers at ARM TechCon are summarized here.

Richard Goering

Photo by Joe Hupcey III

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