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GLOBALFOUNDRIES DRC+ Donation: New Era for DFM Standards?

Comments(0)Filed under: Industry Insights, lithography, DFM, Virtuoso, Encounter, Si2, Global Foundries, DRC, GlobalFoundries, DRC+, pattern matching, yield, DRC Plus, OpenDFM, design rules, manufacturing, hot spots, Si2 conference, DFM Coalition, DFMC

DRC+, a pattern-matching design for manufacturability (DFM) technique developed by GLOBALFOUNDRIES in collaboration with Cadence, is heading for standardization through the Silicon Integration Initiative (Si2). As announced Oct. 20 at the Si2 Conference, GLOBALFOUNDRIES has donated DRC+ data structures to the Si2 DFM Coalition (DFMC), which will incorporate this technology into the emerging OpenDFM standard.

Currently aimed at 28nm, DRC+ is a pattern-based methodology that can be run "in design" by chip design teams well before tapeout. It goes beyond traditional design rule checking (DRC) by using a 2D pattern-matching approach to identify layout patterns that could be difficult to manufacture. As noted in a previous Industry Insights blog post, DRC+ rules are comprised of a rule detracting pattern to avoid and a recommended DFM rule to follow.

Although it doesn't sacrifice accuracy, DRC+ can be hundreds or thousands of times faster than traditional DRC or simulation. In an example cited in a recent blog post on in-design DFM signoff, a 300micron2 block that was designed in the Cadence Virtuoso environment was checked using DRC+.  It took around 5 seconds to find 23 hot spots and fix all of them. Running model-based simulation on the same block took around 8-10 minutes.

DRC+ uses a library of yield-detracting patterns and DFM rules. EDA tools consume those libraries and run DRC+ in pushbutton mode. Some tools that support DRC+, including the Cadence Virtuoso and Encounter environments, offer automatic fixing, as shown below:

Adding to an Open Standard

OpenDFM, meanwhile, is an open-source, extensible format that describes verification intent for leading process nodes, including conditional rules and ranges of acceptable values. Cadence has implemented OpenDFM rules in its Physical Verification System. Si2 released OpenDFM version 1.1 in May 2011.

At the Si2 Conference, Jake Buurma, vice president for West Coast operations for Si2, noted that OpenDFM checks patterns, not design rules. Why? Design rules, he said, are prescriptive - they result in a "pass" or "fail," but designers can't find marginal or robust patterns. Patterns, on the other hand, are descriptive. A pattern-based verification approach can improve marginal patterns and recommend robust patterns.

Buurma said that OpenDFM currently has a library of around 100 patterns now and wants to increase it - and that's where DRC+ comes in. "DRC+ will provide the infrastructure for thousands of patterns," he said.


Vito Dai, senior member of technical staff for DFM at GLOBALFOUNDRIES, described the rationale and history behind DRC+. He noted that conventional design rule checking does not guarantee yield due to context-dependent effects. Designers can use model-based simulation or recommended design rules, but this brings printability verification into the design flow. DRC+ is an alternative that makes it possible to identify patterns that cause DFM problems - and it can run 10,000 times faster than simulation, he said.

What exactly is GLOBALFOUNDRIES donating? "Today, GLOBALFOUNDRIES is announcing the donation to Si2 of the complete set of data structures for DRC+ patterns, including the XML representation we use, XSD files, examples and user documents, so this capability can be standardized in the industry," Dai said.

Dai noted that the foundry intends to extend DRC+ up to 40nm and down to 20nm, with support for double patterning at 20nm. He also noted that GLOBALFOUNDRIES uses the Cadence pattern classification tool. At this time, he said, the four leading IC place and route vendors all support DRC+.

 "Cadence is a strong supporter of Si2's DFMC program, as well as the OpenDFM technology," said Ken Potts, product marketing director at Cadence. "As a co-inventor of DRC+ and an implementer of OpenDFM in our physical verification tools, Cadence is working hard to make sure designs can be verified at advanced process nodes."

Richard Goering

For Further Information

Blog post: How DRC Plus Makes DRC Easy at 28nm

Blog post: "In Design" DFM Signoff - the Inside Story

Archived webinar: DRC+ Now: Early DFM Signoff in the Custom Implementation Process

Archived webinar: DRC+ Now: Early DFM Signoff in the Digital Implementation Process


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