Home > Community > Blogs > Industry Insights > ddr phy interface dfi 3 0 freedom of choice for soc design
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the Industry Insights blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

DDR PHY Interface (DFI 3.0) Spec – Freedom of Choice for SoC Design

Comments(0)Filed under: Industry Insights, SoC, IP, VIP, memory, DRAM, system on chip, PHY, DDR4, controller IP, PHY IP, DFI 3.0, DDR PHY, controller, DDR PHY Interface, DFI, MacLaren, DFI Technical Group

To implement DDR4 memory in a system-on-chip, you'll need both memory controller IP and PHY IP. If there's a standard interface between the two, you won't be locked into a particular controller/PHY combination for future designs. That's why the newly released DDR PHY Interface (DFI 3.0) specification is important news for anyone considering a DDR4 memory implementation.

The DFI 3.0 specification was announced today (Sept. 19, 2011) by the DFI Technical Group, an independent standards body launched by Denali Software in 2006. Participants in the group include ARM, Cadence, Intel, LSI, Samsung, ST-Ericsson, and Synopsys. At the same time, Cadence announced DFI 3.0-compliant design and verification IP.

The chairman of the DFI Technical Group is Denali veteran John MacLaren, now member of consulting staff at Cadence. I recently talked to MacLaren to get some background on the group, the DFI specification, and what it all means for IP and SoC designers.

Basically, the DFI specification defines an interface protocol between memory controller logic and PHY interfaces, with the goal of reducing integration costs while improving performance and throughput. The protocol defines the signals, timing, and functionality required for efficient communication across the interface. The specification does not place any restrictions on how the memory controller interfaces to the system design, or how the PHY interfaces to the memory devices. The DFI interface does not define the implementation details within either the memory controller or PHY - only the interface.

Too Many PHYs

Denali initiated the DFI effort, MacLaren said, because the company was offering a DDR controller and had to "custom integrate" that controller with an increasing number of third-party PHYs. "You can't have one PHY that meets everybody's needs," he said. "Based on the amount of experience and manpower required to do each integration, we said, why don't we just come up with a standard interface we can use with all customers?"

The standard interface is obviously important for controller and PHY IP developers, because they don't have to do custom integrations for each PHY. But it's also important for SoC designers, MacLaren said, because they won't get stuck with a controller that will only interface to a PHY from one provider. Cadence today offers integrated DDR IP solutions that include both controller and PHY, including the first commercial DDR4 IP solution, but as MacLaren noted, "we can't develop a PHY for every single technology. There are way too many processes. We want our controller to work with everybody's PHY."

A DFI 1.0 specification was released in 2006, followed by DFI 2.0 in 2008. These specifications today are supported by nearly every major memory controller and PHY IP supplier. They have been downloaded by 600 "entities" (individuals and companies) with 3,100 total downloads. The specifications are available to anyone through a simple click-through legal agreement.

Enabling DDR4

The new DFI 3.0 specification is a crucial enabler for DDR4, an emerging memory standard with proposed data rates up to 3.2 Gbits/second per pin. It adds several capabilities to previous DFI standard releases, including:

  • CRC error detection (new in DDR4)
  • New commands and address pins associated with DDR4
  • Data bus inversion (for noise reduction)
  • An enhanced DDR training interface with write leveling, data eye training, and gate training

In addition to contributing to the specification, Cadence will support DFI 3.0 across its DDR controller IP, DDR PHY IP, and as part of the Cadence Verification IP Catalog. Meanwhile, anyone interested in downloading the specification or participating in the standards effort can visit the DFI Technical Group web site.

Richard Goering

 

 

Comments(0)

Leave a Comment


Name
E-mail (will not be published)
Comment
 I have read and agree to the Terms of use and Community Guidelines.
Community Guidelines
The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.