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Design for Test (DFT) – New Challenges at Advanced Process Nodes

Comments(0)Filed under: Industry Insights, RTL Compiler, DFT, ITC, ATPG, International Test Conference, 28nm, test, 20nm, 3D IC, 3D-IC, Encounter Test, MBIST, delay faults, SmartScan, stuck-at, design for test, Logic BIST, BIST, transition faults, faults, memory BIST, bridging faults, test compression

Design for test (DFT) doesn't get a lot of press these days, which is unfortunate, because the demands of DFT are dramatically increasing as designers move to smaller lithography nodes. New fault types, test compression, and faster automatic test pattern generation (ATPG) are becoming critical. To get a handle on what's happening in DFT these days, I talked to Mike Vachon, group director of the Cadence Encounter Test product, as he was preparing for next week's International Test Conference (ITC) in Anaheim, Calif. Sept. 18-23, 2011.

"The complexity and the amount of effort that DFT and ATPG take is really growing quickly as designs move to smaller lithographies," Vachon said. He noted that companies are finding they need a lot more DFT expertise, and that DFT IP is becoming vastly more complex, leading to an increased reliance on EDA vendors to generate, validate, and insert that IP during the design process.

Don't Get "Stuck" at Lower Process Nodes

Until recently, designers have focused mostly on static, stuck-at-1 and stuck-at-0 defects. At 45nm, Vachon noted, delay faults begin to become important. At 28nm and 20nm delay faults dominate the defects that customers see. Delay faults (or transition faults) can result in "slow to rise" or "slow to fall" defects. "The tests required to detect those kinds of defects are complex, and they require at-speed test clocking," Vachon noted. "This drives the need for special test clocking IP during DFT insertion."

Further, Vachon noted, bridging faults are becoming more prominent at 28nm and below. These are defects that tie two wires together that should not be coupled. Thus, a new bridging fault model is required, along with related test vector generation.

Test compression, which results in test vector sets that can be applied in less time (and thus for less cost), has been around for some time. But it's becoming more critical at lower process nodes because the complexity of test vector sets is skyrocketing. Further, compression is difficult in low-pin count architectures, which are common in the "big A, little D" mixed-signal design world.

There are other concerns as well. Because test vector sets at 28nm and below are getting huge, ATPG for large SoC designs is slowing. It could take 3-4 weeks to generate test vectors for a large design, "not a manageable amount of run time," as Vachon said. And some IC design environments still wait until after synthesis to insert DFT structures. This results in problems with timing, power, and routability.

Tested Solutions

At ITC, Cadence will show how it is responding to some of these challenges. One response actually took place several years ago, when Cadence decided to move all of its DFT insertion and verification capabilities into the RTL Compiler synthesis tool. Thus, tasks such as scan chain insertion, compression, clock generation for at-speed test, and memory BIST are accomplished during, not after, synthesis. While ATPG occurs in the Encounter Test product, RTL Compiler leverages the ATPG environment to estimate test coverage and insert test points.

One new capability that Cadence will discuss at ITC is logic BIST. While BIST is frequently applied to memory, logic BIST saw most of its use 10 or 15 years ago, when it was used for processor design. But now - it's back! Vachon pointed to a "huge increase in demand" for logic BIST over the past year or two in the automotive market, as well as for some consumer products. (Cadence has manually generated logic BIST macros for a long time; what's new now is the ability to insert a standard macro as part of the synthesis process).

Another new capability is SmartScan, a very low pin count compression architecture that will be especially helpful for big A, little D designs. In this market segment, a device might only be able to spare 4 or 5 pins for test. SmartScan essentially puts a wrapper around an existing compression architecture that allows designers to control a test compression macro with a very small number of pins. Here is how it works in the RTL Compiler and Encounter Test environments:

Finally, Cadence is presenting an improved, distributed ATPG capability that runs in parallel computing environments. Vachon said that it can produce a 13X speedup with 16 CPUs, or a nearly 4X speedup with 4 CPUs.

Cadence at ITC

Cadence activities at ITC include:

  • MBIST Tutorial, Monday 8:30-4:30 pm - includes paper on recent developments in fault modeling
  • Corporate presentation, Tuesday 2:20 pm, Exhibit Hall
  • Advanced Industrial Practices session, Tuesday 4:00 pm - paper titled "How Real are Small Delay Defects? A Silicon Case Study"
  • Poster Session, Wed. noon-2:00 pm -Automation of 3D IC DFT, co-presented by Cadence, imec, and TSMC
  • 3D IC test workshop Thursday and Friday -- demo based on the Cadence/imec test architecture I blogged about recently.

Further information about these activities is available here.

Richard Goering



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