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Webinar: Easing the Pain of FPGA-Based Prototyping

Comments(0)Filed under: Industry Insights, Palladium, EE Times, emulation, webinar, Cadence, Altera, FPGAs, FPGA-based prototyping, System Development Suite, Rapid Prototyping Platform, rapid prototyping, RPP, Jaeger, Stratix, Quartus, Simpson, bring-up, software developmentNearly every digital system-on-chip, ASIC or ASSP is prototyped in FPGAs, most typically for pre-silicon software development and debugging. The problem is that it can take months to get the prototype up and running with a functionally equivalent design. But there are easier ways to develop FPGA-based prototypes, according to a webinar now available for viewing at EE Times.

    The webinar is titled "FPGA-based prototyping is hard to do - or is it?" Speakers are Juergen Jaeger, senior product marketing manager at Cadence, and Phil Simpson, senior manager for software technical marketing at Altera. They discuss why FPGA-based prototyping is needed, how existing approaches fall short, and what's needed to speed prototype bring-up times. They also provide some information about the Cadence Rapid Prototyping Platform and the Altera Stratix IV 820 devices and Quartus II software used within it.

    It's All About Software

    Jaeger, who spoke first, noted that FPGA-based prototyping is all about software. "In many cases, getting to tapeout is not the biggest problem we are facing any more," he said. "Software has started to dominate development costs and schedules. It is therefore critically important to get a head start in developing software." Jaeger cited an IBS study that showed that a 9-12 month delay in system integration and bring-up can result in a revenue loss of $50 million to $100 million.

    So where does FPGA-based prototyping fit? Early in the design, while the hardware is still in flux, software developers may use simulation and emulation. "When the hardware design matures, and it's time to start pre-silicon software development, that's where FPGA-based prototyping enters the picture," Jaeger said. "You want to have somewhat stable RTL before implementing the design in a prototyping system."

    The problem, however, is that it takes too long to implement the SoC or ASIC design into an FPGA prototype. This is partially because it requires changes to the RTL code, and partially because there is no easy translation between simulation and emulation to FPGA-based prototyping. Jaeger identified the following steps in prototype bring-up:

    • RTL preparation, memory modeling, compilation, synthesis - may take 5 weeks
    • Automatic or manual multi-FPGA partitioning - may take 2-4 weeks
    • Functional model validation (does the prototype behave identically to the original design?) - 4 weeks
    • In-circuit bring-up - 2 weeks

    This process can add up to 3 months or more. What can be done? Jaeger said that the following combination of capabilities can get this time down to 4 to 5 weeks:

    • A proven ASIC compilation flow requiring minimal RTL changes
    • Automatic ASIC to FPGA memory conversion
    • Fast synthesis
    • Fast, automated multi-FPGA partitioning
    • Optional guided partitioning
    • Using Cadence Palladium emulator to validate and debug functionality, finding bugs before going through lengthy FPGA place and route iterations

    These are the kinds of capabilities available in the Rapid Prototyping Platform, and Jaeger went through a brief overview of the hardware and software that comes with that platform. He said that it's the only "complete" FPGA-based prototyping solution today, and that it is "really addressing the challenges and pain points that prototype users are facing - bring-up times, validation of the model, debugging, and flow integration."

    Rapid Prototyping Platform

    The FPGA Perspective

    Simpson provided an Altera view of FPGA-based prototyping (which he also called "ASIC prototyping") and what's needed to make it successful. He identified the following requirements that designers will need to consider about FPGA-based prototyping:

    • FPGA silicon

                --How much of my design can I fit per device?
                --How fast can I get the design to run?
                --Do I have enough on-chip memory for ASIC specific functions?
                --How do I ensure design security when deploying systems externally?

    • Software tool flow

                --How similar is my FPGA tool flow to my ASIC tool flow?
                --What design changes are required?
                --How do I debug my design within the FPGA?

    • Board-level design

               --How do I design a board with multiple FPGA devices?
               --How do I partition my design between multiple FPGA devices?

    "A combination of the Altera Stratix IV device and the Quartus II software from Altera, bundled with the Cadence Rapid Prototyping Platform, provides a fast and efficient solution that will meet all the requirements I've mentioned," Simpson said. He then went on to describe the Stratix IV 820 device and its features, including logic, memory, and DSP resources; high-performance core and I/Os; clocking resources; and programmable low-power technology. Simpson reviewed key features of the Quartus II software including timing analysis, physical synthesis, and multiprocessor support.


    The webinar was well-attended and the questions kept coming right up to the end. Here's a brief sample of the questions that came up for Jaeger and Simpson.

    Can the Rapid Prototyping Platform be used without Palladium hardware?
    What other Altera families can be used for prototyping?
    What's the best way to get started in FPGAs?
    Does Quartus do clock gating optimization?
    What's the scalability of Palladium and the Rapid Prototyping Platform?
    How easy is it to verify a PHY based design?
    Does Palladium support the integration of analog components?

    Note: This webinar did not provide an overview of the System Development Suite, which comprises four development platforms including the Rapid Prototyping Platform. For more about the entire suite and how it all works together, and fits into the EDA360 vision, see my blog post from last May.

    A repeat version of this webinar, with timing geared to European audiences, will be held Sept. 14.

    Richard Goering


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