Time for a mainstream revolution? That was the title of a lively panel discussion at the Global Technology Conference (GTC) Aug. 30. Panelists noted that there's still a lot of activity at 65nm and above. They discussed why this is true, whether mature nodes can be retrofitted with new capabilities, and what impact older nodes are having on EDA and silicon IP.
The panel was moderated by Ed Sperling, editor of System-Level Design, and featured these panelists:
- John Heinlein, vice president of marketing, ARM
- Walter Ng, vice president of IP ecosystems, GLOBALFOUNDRIES
- Vishal Kapoor, vice president of marketing, SoC Realization, Cadence
- Naveed Sherwani, CEO, Open-Silicon
- Jeff Lukanc, senior design director, Integrated Device Technology
This was the second of two panels at GTC. I blogged about the CEO panel and GLOBALFOUNDRIES 28nm and 20nm plans previously.
Here are some of the questions and answers that came up at the panel.
What is the mainstream node today?
Heinlein: A lot of high-volume applications are at 55nm and older. "Even though the sexy talk is about the very leading edge, last year 75% of our royalties came from cores and other IP available in 2006 and earlier."
Ng: "65nm is the workhorse and the brunt of our volume for the past couple of years. A lot of customers are doing very cool, very relevant things. This is what pays the bills."
Kapoor: 65nm pays the bills as much as 28nm and 20nm. "We respect that 65nm is the mainstream node."
Lukanc: A lot of our new designs are ramping at 65nm, and we're looking at older technologies. If we're running at 30V that may take a 130nm or 180nm process.
Sherwani: I recently visited 10 different fabs in China. Some haven't made it to 65nm or even 90nm. They're developing silicon for high-speed trains.
Why is there so much design activity at older nodes?
Heinlein: Everybody looks at the applications processors in smartphones, but there are power management controllers alongside them, and sometimes RF or mixed-signal chips. Also, people are using value-added (older) processes for low leakage or high voltage.
Kapoor: If you have to integrate a lot of analog/mixed-signal capability, with simple digital capabilities, a mature node makes perfect sense. Now what you'll have to learn to do is integration.
Lukanc: "With older technologies, masks are quite cheap. If you're reusing IP you can develop a product with very little engineering development."
Sherwani: A lot of analog silicon will ship out of China, and it's all older nodes.
Can value be added to older process nodes?
Ng: Today, in most of our 200mm fabs, we develop value-added modules on top of the logic. Those modules are focused on particular market segments. For example, we have a big focus on high voltage and power management. We look at how we can bring more application-specific solutions onto the baseline logic, which is a commodity offering at this point. "The incremental investment to develop and bring up value-added modules is nothing compared to development at the leading edge."
How does the use of older process nodes impact IP?
Heinlein: "In most cases base IP works. In some cases we have to augment it. In the old days, people didn't care about leakage at 180nm, but now we're putting things like power management back into 180nm."
Kapoor: Innovation at the leading nodes is going to drive benefits back into EDA tools, IC processes, and design techniques. Following a 28nm IP development, "as we waterfall back to 40nm and 65nm, we find we have better IP."
Will 3D stacking impact the use of older process nodes?
Heinlein: "3D packaging will probably help people choose not to scale RF to 20nm. They'll find a sweet spot at 40nm or 65nm."
Kapoor: 3D technology by itself is not the answer; the question is to find out where it makes sense. One such place may be tablets, where you have an SoC "talking in very high bandwidth to memory."
What are the impacts on EDA tools?
Heinlein: People designing at 130nm or 180nm may have a tool base they want to reuse. One challenge is using older tools and new IP. Another challenge occurs when people want to use new tools on older nodes.
Sherwani: "I believe EDA companies are very focused on physics. They don't have the mindset of asking, is it possible to do a 180nm design in one day? Open-Silicon is involved in many derivative designs. The mindset required is different from what we have today."
Kapoor: In our core EDA business, we spend a lot of time on engineer efficiency. You will see capabilities coming out that address that.
If power was not an issue at 180nm, why is it becoming an issue now?
Heinlein: "The bar always moves. People are looking at applications that are much lower power than before. You need to have power management chips alongside other chips."
If foundries are working at older nodes, what does the ecosystem look like?
Sherwani: Fabs in China do everything themselves. They are very focused on a certain area and they have 10, 20, or 30 pieces of in-house IP.
Heinlein: People are very comfortable with niche markets. People are shipping 8051-based applications and enabling modern software development.
Ng: A key message from GLOBALFOUNDRIES is that the foundry business is not just about providing silicon. It's about the service you provide. We struck a relationship with Rambus quite early in 28nm, and we had to change the way we support them and do a two-way dialog so they understood our solutions. Foundries today are not just about silicon.
A closing comment
As noted in my previous blog post, GLOBALFOUNDRIES is indeed moving from "offerings" to "solutions." Similarly, Cadence has moved from point tools to end-to-end Silicon Realization solutions. Older process nodes remain very active, but the old ways of doing foundry, EDA and IP business are undergoing profound change.