The 28nm node is "fully enabled" and ready for production ramp-up, and 20nm early adopter flows are available now, according to GLOBALFOUNDRIES executives at the Global Technology Conference (GTC) in Santa Clara, California Aug. 30. In several morning sessions, speakers updated the company's plans for 28m and 20nm and offered some speculation about 14nm and beyond.
On the eve of the conference, GLOBALFOUNDRIES announced a "significant milestone" towards market readiness of its 20nm process by successfully taping out a test chip using flows from Cadence and other EDA vendors. Separately, Cadence announced work with GLOBALFOUNDRIES and Rambus that resulted in a 60X design for manufacturability (DFM) signoff speedup at the 28nm node (more on this in Steve Leibson's blog post).
Key points made by GLOBALFOUNDRIES executives included the following:
- A new 28nm high-k metal gate (HKMG) technology, 28nm-LPH, was developed in collaboration with Samsung to serve high-performance mobile applications. It complements the existing 28nm-SHP (high performance) and 28nm-SLP (low power) technologies.
- A single 20nm technology family, 20nm-LPM, will serve most applications that don't need extremely high performance.
- After using a "gate first" HKMG approach at 28nm, GLOBALFOUNDRIES will shift to "gate last" HKMG at 20nm.
Ajit Manocha, GLOBALFOUNDRIES CEO, said in his opening keynote that products using the company's 32nm HKMG technology are "on store shelves now," 28nm is "fully enabled and ready to ramp," and that 300mm wafer capacity is expanding rapidly. In 2012, he said, 28nm will ramp to full production and 20nm will begin fabrication at the under-construction Fab 8 in New York state.
A Detailed Roadmap
Gregg Bartlett, senior vice president of technology and integration engineering at GLOBALFOUNDRIES, explained that his company will provide 28nm and 20nm offerings in three key market areas:
The GLOBALFOUNDRIES web site already describes 28nm-HP (High Performance) and 28nm-HPP (High Performance Plus), as well as 28nm-SLP (Super Low Power). The new technology is 28nm-LPH, developed with Samsung. Aimed at high-end mobile computing, it offers better performance than SLP and more power reduction than HP. LPH capabilities include a 1V overdrive for higher performance and LLSRAM and ultra-high Vt for leakage reduction. It claims to cut active power by up to 60% at the same frequency, or boost performance by 55% at the same leakage level, compared to 45nm.
Bartlett said that the 28nm gate-first HKMG technology provides true scaling relative to 40nm, with a 100% density increase, up to 40% increased speed, and up to a 40% reduction in energy and switching at nominal operating voltages. It claims a 10-20% area reduction compared to gate-last 28nm. Multiple 28nm product tapeouts are underway, library and IP solutions are ready, and a fully enabled ecosystem (including EDA and IP) is in place. "28nm is ready for prime time," he declared.
20nm promises even more gains compared to 28nm - 2X gate capacity, up to 35% performance increase, and a potentially more cost-effective solution once full production is underway in 2013. But there are some changes. One is the requirement for double patterning on some metal layers, and here, Bartlett said, "the trick is to set the right design rules to enable scaling without increasing the number of double patterning layers required."
Also, he said, 20nm demands a different HKMG approach, and after a "detailed analysis" GLOBALFOUNDRIES settled on a gate-last approach. In short, the density and scaling benefits of gate-first HKMG no longer apply at 20nm because of lithography restrictions.
At 20nm, the LPM technology will serve a broad range of applications, from low-power/cost-sensitive mobile devices to high-end mobile applications and wired desktop applications. It's bulk technology with a nominal Vdd of 0.9V and overdrive support. 20nm-SHP will provide an additional high-performance option.
What's coming up below 20nm? Bartlett pointed to multi-gate FinFETS, source mask optimization, ETSOI silicon-on-insulator technology, and new approaches to packaging. He also said that GLOBALFOUNDRIES will install EUV (extreme ultraviolet) lithography at Fab 8 in the second half of 2012. He mentioned a new agreement with Amkor that will lead to increased support for 2.5D and 3D IC packaging. Further out still, he said GLOBALFOUNDRIES is working with academia to figure out the "ultimate replacement" for CMOS.
Designing at 28nm and 20nm
So how are chip design teams going to work with these promising but very challenging process nodes? If there was any one consistent theme at GTC, it was the need for collaboration among a broad ecosystem including EDA, IP, mask companies, outsourced assembly and test (OSAT), and design services. "Collaboration is key to our success," Manocha said.
Mojy Chian, senior vice president for design enablement at GLOBALFOUNDRIES, talked about his company's move from "offerings" to "solutions" - for example, offering fully integrated process design kits (PDKs) instead of just supplying technology files, using integrated pattern-based DFM instead of relying on traditional design rules, and providing silicon-verified "platform based" IP as opposed to component IP. At 20nm, he noted, GLOBALFOUNDRIES will offer some new capabilities, including design rule checks for image decomposition (double patterning), density patterns, uniformity control, and a graphical design rule manual.
"We're working with our [EDA] partners to provide front-to-back flows with GLOBALFOUNDRIES silicon validation," Chian said. He noted that GLOBALFOUNDRIES will provide signoff modules for physical verification, DFM, and extraction. He also spoke about "design enabled manufacturing" (DEM), which is kind of the flip side of DFM - while DFM brings manufacturing information into design, DEM brings design information into manufacturing, providing not only GDSII but a "knowledge database."
"We are ready at the 28nm node," Chian said. "All the components are ready go to, and there is significant customer engagement." He noted that comprehensive PDKs and silicon-validated IP are available today. "We are also ready for early engagement at 20nm," he said. An early version of the PDK is out, early test chips are targeting multi-fab shuttles, and "advanced stage discussions" are underway with IP providers for both foundation and complex IP.
The GTC conference packed a lot more into one day, including a CEO panel, a panel on mature process nodes, and a Cadence presentation on 20nm. I'll have more coverage in upcoming blog posts.
Related blog posts
Whitepaper Summary: How to Succeed at 20nm
Video: Easing the Challenges of Double Patterning at 20nm
Q&A: Samsung's Ana Hunter Offers Advance Look at 20nm
DAC Panel: 20nm is Tough, But Not a Roadblock
Double Patterning - A Double Edged Sword?