The upcoming 20nm process node promises tremendous advantages in power, performance and area - but it's also very challenging in terms of design complexity, lithography, and manufacturability. A newly published whitepaper from Cadence, summarized here, sets forth an approach that can mitigate the challenges of 20nm.
While each new technology node has its challenges, the move to 20nm presents more than most. One much-discussed challenge is double patterning, which uses two or more masks to image a single layer. It's needed in order to get current lithography equipment to print correctly at a node where features are one-tenth the wavelength of light used in lithography. The whitepaper describes the design challenges of double patterning and the tool support it requires.
Intent, Abstraction, Convergence
So what's new at 20nm, aside from double patterning? According to the whitepaper, "what is unique to 20nm is the deep and complex dependency of manufacturing and variability issues on top of the timing, area, and power issues designers were already facing." As a result, "everything about 20nm design and implementation is interrelated and inter-dependent in complex ways." The traditional iterative and sequential design flow will not work - a holistic flow, in which each stage is interdependent, is needed.
As noted in the EDA360 definition of Silicon Realization, three capabilities bring this holistic flow together. They are:
- Unified design intent, making it possible to use the same timing, area, power, and manufacturing constraints for each tool, from chip planning to signoff.
- Abstraction, which reduces complexity in order to improve productivity in tasks such as design exploration, prototyping, verification, and layout.
- Convergence, which enables a successful tapeout by running signoff checks throughout the flow.
The whitepaper provides practical examples of each. For example, it shows how unified design intent facilitates low-power design and makes layout-dependent effects (LDE) more predictable. It illustrates how abstraction supports greater complexity and capacity (example: a pattern-based approach finds potential yield problems 10,000 times faster than printability simulation). And it describes how convergence throughout the flow, with signoff checks run at multiple points, paves the way to successful silicon.
Making Double Patterning Work
The whitepaper also provides a number of insights into double patterning and what's needed to make it successful. It notes that double patterning requires the successful decomposition of the design layout into multiple masks, and that this places some restrictions on the layout. Managing double patterning cannot be left to a final signoff tool; it must take place throughout the flow.
Double-patterning aware placement
More specifically, placement tools must understand that certain cells cannot be placed next to one another (both because of double patterning and LDE). Routing tools must model the way a layer will be separated into two layers, or "colors," that can be recombined in lithography. Physical verification tools need to ensure the final decomposition is accurate.
The whitepaper concludes that "keeping design intent in mind and leveraging smarter abstraction methods and technologies, advanced node design teams will be able to achieve convergence and deliver timely silicon." At 20nm, the whitepaper notes, "holistic design flows offer the only practical, predictable path to working silicon." The whitepaper is available here.