Double patterning lithography will be essential at 20nm and below until at least 2014, according to Lars Liebman, distinguished engineer at IBM. But it need not be a huge burden for engineers. In a talk at the Cadence booth at the Design Automation Conference in June, and newly available in the video clip embedded below, Liebman described how double patterning works, what design challenges it poses, and how IBM and Cadence are working to minimize the challenges.
According to Liebman, the much-awaited extreme ultraviolet (EUV) lithography won't be in volume manufacturing until 2014. Meanwhile, the 20nm process node will be available for production in 2012. Double patterning, which splits designs into two or more masks, will be "absolutely required" at 20nm and 14nm until EUV is in volume production, Liebman said. "We have no alternative. We need to keep scaling. We can't slow down," he said.
Liebman based his talk on three simple premises:
- Hiding the complexity of double patterning is a bad idea that will lead to suboptimal designs.
- Even so, we can make decomposition (splitting the design into separate masks) very transparent, by publishing "split level design rules."
- In addition, we need well-integrated, double-patterning aware design flows.
The bottom line, Liebman said, is that "putting our cards on the table and making this all transparent to the design community is a good choice."
A Closer Look at Double Patterning
In the video, Liebman notes that double patterning requires two exposures that are optically decoupled from each other. One technique, called "pitch splitting" or "litho-etch, litho etch," involves two masks with two separate process steps. Another technique, "sidewall spacer" or "self-aligned" double patterning, makes use of sidewall image deposition to form spacers. The video includes presentation slides that show how these approaches work.
In either case designers have to do the two-color mapping that determines the decomposition, and that's where the design complexity comes in, Liebman explains. The best solution, he argues, is to publish split-level design rules.
In the video, Liebman notes that the decomposition process "can be reduced to practice with Cadence tools." He also talks about the work that IBM is doing with Cadence in double-pattern aware routing.
"It's not feasible to route the chip and then check for coloring conflicts -- you'll end up with millions of conflicts," he said. "By understanding split-level design rules, you can engineer double-pattern enhanced routing solutions, and that's an example of what we're working on with Cadence in their routing platform." This work has involved exploring different levels of restriction for design rules.
To view the video, click on the icon below, or click here if it does not open.
Related blog posts
Double Patterning - A Double Edged Sword?
Q&A: Samsung's Ana Hunter Offers Advance Look at 20nm