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Free Webinars Explore Advanced Functional Verification Techniques

Comments(0)Filed under: Industry Insights, specman, Analog, verification, Metric-driven verification, Functional Verification, Formal, UVM, SystemVerilog, assertions, assertion synthesis, coverage, C++, metrics, verification webinars, assertion-based simulation, scoreboarding

UVM, assertion-based simulation, metric-driven verification, assertion synthesis, formal scoreboarding -- these are just a few of the advanced techniques that can improve your verification productivity. To help you learn about such techniques, Cadence is offering a series of nine free one-hour webinars that run from August 23 to December 15.

These webinars are highly technical and focused on "how to" topics. They are presented by Cadence domain experts, and include demonstrations where applicable. The intent is to help listeners discover best practices for tackling tough verification challenges, learn new applications and methodologies, get answers to questions, and boost verification productivity and closure.

Further information about the webinars is located at the Cadence functional verification events web site. This site also has links to nine archived functional verification webinars completed in the first half of 2011. For registration, click here. The nine new webinars are briefly described below. Click on the time and date link to see more detail about each webinar.

Finding the Bugs in Your UVM Haystack
23 Aug 2011 9:00 AM (PDT)     

This webinar will help you see how GUI-based debug can improve your productivity over embedded print statements enabling you to visualize your UVM class structure, data, transactions, and more. It will focus on the debug capabilities in SimVision that will help you find those bugs no matter where they are in the haystack of data.

Ending the Debate - Apples or PC's? e or SystemVerilog?
08 Sep 2011 9:00 AM (PDT)      

With HVL standardization, the importance of consistent, open, and interoperable methodologies are more evident than ever, and verification engineers can finally freely choose. Just like choosing Apples or PCs, understanding the pros and cons of both languages will end your debate of which language to choose. This webinar will also technically compare and contrast UVM e and UVM SystemVerilog to assist you in choosing which language would best meet your verification needs.

Applying Digital Verification Methodologies to Analog Design
15 Sep 2011 9:00 AM (PDT)     

This webinar will discuss how to approach analog block integration regardless of abstraction level (Spice, AMS models, real number models) and how to increase your verification quality and productivity using a metric-driven approach. 

Automate Assertion Generation for Simulation, Formal and Emulation Flows
13 Oct 2011 9:00 AM (PDT)     

In this webinar, Cadence and NextOp Software will show how assertion synthesis enables a progressive, targeted verification process, allowing design and verification teams to more easily uncover corner-case bugs, expose functional coverage holes, and increase verification observability. A demonstration will reinforce the concepts learned during the session.

Oceans of Expertise Connecting the UVM to Sea (C /C++/SC)
20 Oct 2011 9:00 AM (PDT)     

This webinar will share the steps you need to prepare, build, and debug the mixed-language verification environment. It will focus on the methodology for mixed-language environments, bringing the Incisive Enterprise Simulator into the discussion primarily to describe advanced debug techniques.

What Metrics Matter – A User’s Perspective on Coverage
03 Nov 2011 9:00 AM (PDT)      

The webinar will share the details of what metrics matter during the different stages of verification and how these metrics can be leveraged to reduce the risk of failures in your design. Knowing where to start and how to finish is fundamental to verification success. This webinar will be mostly focused on methodology and not tools; however, some tool-based representative examples will be shown for credibility and reference to the methodology. 

Quickly Find Data Transport Bugs with Formal Scoreboarding
17 Nov 2011 9:00 AM (PST)     

"Scoreboards" have been used in advanced simulation testbench environments for years. In this webinar, we will show how this same concept can be implemented with formal verification tools. Consequently, you will see how to benefit from powerful formal analysis algorithms to automatically test data integrity and root out the spectrum of simple problems to extreme corner cases.

Set Your UVM Runtime Phases to Maximum Power
01 Dec 2011 9:00 AM (PST)     

This webinar will share the steps you need to determine if your UVC really needs runtime phases. If it does, the component is simpler to build and maintain. Assuming you are attending because you do need to apply them, the webinar will provide critical methodology guidelines to maximize the verification power you will derive from runtime phases and help you to avoid common pitfalls as you integrate your UVC into larger system verification environments.

Simplifying Code Coverage Analysis: Automatically Separating the Wheat from the Chaff
15 Dec 2011 9:00 AM (PST)     

In this webinar, we will show how new automation and a revolutionary "case-splitting" methodology can help you separate the wheat from the chaff-the "reachable" versus the "unreachable" code coverage holes. A demonstration will reinforce the concepts learned during the session.

Richard Goering

 

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