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Cadence at Flash Memory Summit: Design Panel, PCIe Storage, and Free Pizza and Beer

Comments(0)Filed under: Industry Insights, DRAM, flash, flash memory, memory models, memory controller, memory IP, PCI Express, Flash Memory Summit, Gen3, controller IP, non-volatile, NAND flash, PCIe

The Flash Memory Summit, held Aug. 9-11 in Santa Clara, California, is the place to be for anyone designing with flash memory components or IP solutions. In the past, Denali Software was a sponsor of this conference; this year, Cadence is a Platinum sponsor and is actively involved with the conference program.

Why the interest? Following the Denali acquisition, Cadence is a provider of flash memory IP solutions, including a NAND flash controller and NAND flash PHY. Cadence, in fact, is placing a heavy emphasis on memory (DRAM) and storage (NAND flash) controller IP as part of its SoC Realization strategy, as I noted in a blog post this spring.

In booth 206, Cadence will be showing its flash memory controller solutions, as well as low-density parity check (LDPC) error correction technology, host system interfaces including PCI Express solutions, and hardware/software integration solutions including verification IP and memory models. Cadence is also participating in two technical sessions described below, and is sponsoring a "Beer, Pizza and Chat with the Experts" session at 6:00-7:30 pm Tuesday, Aug. 9.

Panel: Non-Volatile Design Practices and Methodologies
Session 302, Thursday Aug. 11, 8:30-9:40 am

This panel is organized and moderated by Bob Pierce, senior technical marketing manager for SoC Realization at Cadence, and includes speakers from Cadence, Altera, and Pliant Technology. The panel will look at the architectural challenges presented when designers transition to next-generation products that target higher IOPs (input/output operations per second) across channel operations and CPU workloads. Additionally, it will look at the integration of hardware and firmware.

Paper Session: PCIe Storage 2
Session 302, Thursday Aug. 11, 2:00-3:15 pm

Ashwin Matta, engineering director for SoC Realization at Cadence, will present a paper in this session titled "Harnessing PCIe Gen3 Capabilities for Storage Applications." He will present an implementation of the PCIe Gen3 specification with features targeted at maximizing flexibility and data access within a storage subsystem.

Beer, Pizza, and Chat with the Experts
Tuesday, Aug. 9, 6:00-7:30 pm

This unique session is sponsored by Cadence and organized by Tom Coughlin, Coughlin Associates, and Jim Handy, Objective Analysis. It gives attendees a chance to discuss a wide variety of subjects in an informal atmosphere, and to pose questions to experts in specific areas. Tables will be set up for subjects such as SSDs, embedded applications, standards, software, data security, and new technologies and markets. Attendees are welcome to move from table to table. A complete list of table subjects is available at the conference web site.

Be sure to check out the entire conference program at the conference web site. There are nine keynote speeches in addition to panels, tutorials, and paper sessions. On-line registration is available until August 6, and a free "Exhibits and open sessions only" pass gets you into the keynotes and open sessions such as the beer and pizza chat. See you there.

Richard Goering



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