One of the most challenging aspects of 3D-IC development involves the testing of vertical die stacks with through-silicon vias (TSVs). You have to propagate test data up and down through the stack, verify the functioning of TSVs that are too small to probe, and isolate the individual dies you want to test. A recent collaboration between Cadence and the Belgian research institute imec helped ease some of these problems by developing an automated 3D-IC DFT architecture.
The collaboration was announced during the June Design Automation Conference, and I'm sure it received less attention than normal due to the dozens of press releases coming out from EDA vendors that week. To get more information I talked to Brion Keller, senior architect at Cadence.
The collaboration was aimed at both pre-bond (or "wafer") testing, which occurs before the dies are stacked, and post-bond testing, which occurs after two or more dies are stacked. Although difficult, pre-bond testing is important because it's a lot less expensive to find defects before the dies are placed in a stack. Imec is well known for its 3D-IC research, and the collaboration leveraged and extended work already done at imec in 3D-IC test.
Challenges of 3D-IC Test
Keller noted that pre-bond testing is difficult for any die that is not intended to be the bottom die in a stack. Such dies only connect to the dies above or below through TSVs (where the TSVs touch down on micro-bumps on the neighboring die), and the resulting pins and micro-bumps are too small for current probe technology to handle. A middle (or top) die will functionally use TSVs on one side and micro-bumps on the other - there are no traditional I/O pads that testers could probe.
"One thing we're automating is bringing the important test signals out to larger pads," Keller said, "so, we have a chance of doing a wafer test without some really exotic way of probing the device. These pads are used only for pre-bond testing."
During post-bond testing, the only contact you have with the package is through the package pins, and to access those you have to go through the bottom die. "When all the test signals have to go through the bottom die," Keller said, "you can't afford to devote additional signals on the bottom chip just to connect test signals from the package pins to a chip above. You have to come up with a different way of sending test data in and out of the chips above the bottom chip. The essence of the [DFT] architecture is defining a way to get test data to and from any of the chips in the stack without overly consuming a lot of package test signals."
Solution? It's a Wrap
The IEEE 1500 core test standard, currently supported by the Cadence Encounter RTL Compiler product, provides a way to develop "wrappers" that isolate embedded cores inside systems-on-chip for testing. The imec-Cadence DFT architecture uses "3D enhanced" IEEE 1500 die wrappers. Basically, a wrapper provides isolation and boundary-scan elements that allow internal testing of a core or die. It works with scan, BIST or any other DFT technology that may be employed on an individual die. The DFT architecture uses IEEE 1500 boundary scan, but can also work with IEEE 1149.1 boundary scan test protocols.
"When you wrap a chip you're isolating the internals of the chip, so you can test them without having to contact all of the pins on the chip," Keller said. "And you can also go the other way, and talk to the interface of the core or chip without having to scan everything that's inside."
During post-bond testing, you still have to access the bottom die, but you can avoid communicating with any other dies you don't care about. You can also "bypass" the internals of the bottom die if you're communicating with another die. During pre-bond testing, boundary scan gives you the ability to detect values on TSVs that are inputs or outputs to a die (but not the actual value at the end of the TSV). This approach is similar, Keller said, to "reduced pin count testing," a technology that has been around for years.
In the DFT architecture, the IEEE 1500 test wrappers are extended to work in three dimensions. For example, an "elevator" construct makes it possible to send data to dies located above or below a given position. The larger probe pads used on non-bottom dies, mentioned earlier, represent another extension. The DFT architecture doesn't necessarily take a lot of area. Initial results on customer designs showed an area increase as low as 0.2 percent for 3D wrappers.
Another aspect of the Cadence-imec collaboration involved automatic test pattern generation (ATPG). The collaboration developed technology that makes it possible to do an interconnect test for a packaged 3D-IC without needing the full internals for each chip. It leverages an existing capability in Encounter Test for testing multi-chip modules that makes it possible to model only the logic that's needed to run a boundary scan interface within each chip.
The results of the Cadence-imec collaboration will be reflected in upcoming releases of Cadence synthesis and test products. There is more to be done - tester and probe technology also needs to improve. But the important message is that test challenges need not be a bottleneck that delays the mainstream adoption of 3D-ICs.