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Why Cadence Bought Azuro – A Closer Look

Comments(0)Filed under: Industry Insights, ARM, Encounter, EDI, EE Times, Deokar, Silicon Realization, Gary Smith, Rubix, useful skew, propagated clocks, clock trees, PowerCentric, CTS, ccopt, Azurol clock tree synthesis, clock networks, Desharnais, clock concurrent optimization, clocks

Cadence announced July 12 its acquisition of Azuro, a provider of "clock concurrent optimization technology" (ccopt).  But why, given that Cadence already has clock tree synthesis inside the Encounter Digital Implementation Platform? The answer is that Azuro technology goes far beyond clock tree synthesis to provide a new IC physical implementation approach that offers compelling power, performance, and area advantages.

Traditionally, clock tree synthesis (CTS) distributes source clock signals to thousands of data registers, while balancing skew so that signals arrive at almost exactly the same time. A separate step then finishes the placement and the post-CTS physical optimization. Azuro's ccopt technology, in contrast, merges timing-driving placement, "useful skew" clock tree synthesis, incremental physical optimization, physical clock gating, and post-clock tree optimization into a single step. 

The Azuro technology is especially advantageous for GHz-range designs that use embedded ARM processors such as the Cortex-A9 and Cortext-A15. For high-speed processor designs, it has consistently delivered quality-of-silicon results as follows:

  • Power: Clock tree power reduction up to 30%, and total power reduction up to 10%
  • Performance: Improvements up to 100 MHz for a GHZ design
  • Area: Clock tree area reduction up to 30%

When Clocks Go Insane

The existing clock tree synthesis technology in Encounter Digital Implementation System is fully equipped for the majority of designs, according to David Desharnais, product management group director for Silicon Realization. But as process nodes go to 32nm and 28nm and below, and chip speeds need to run at the multi-GHz level, "clock networks become insane," he said.

"There are often well over a hundred clocks that can be branched and merged thousands of times," Desharnais said. "The end result is a dense spaghetti network of clock muxes, clock XORs, and clock generators, entwined with clock gating elements from the highest levels in the clock tree to the lowest levels in the clock tree.  When designers are trying to wring out every possible Hz on the chip, traditional CTS tools fall short. What's needed is a fundamental re-architecture and a new approach to the entire concept of CTS, and that is exactly what ccopt is."

And you can't focus only on clocks, noted Rahul Deokar, marketing director for digital implementation at Cadence. Azuro's ccopt technology, he said, "looks not only at clocks but at the rest of the design in the context of the clock. For high speed designs, clocks have to be designed along with the physical aspects of the rest of the chip."

Cadence is already working on next-generation CTS. So why buy Azuro? "Our work in the area of next-generation CTS is not just about CTS," Desharnais said. "We are rethinking and re-architecting the entire concept of how digital implementation is done end-to-end to achieve the highest performance, lowest power systems on chip.  Azuro's technology is a perfect dovetail into what we're doing here, and through its tight linkage to EDI [Encounter Digital Implementation] System it is providing a big performance, power, and area advantage for our customers."

EDA Success Story

Azuro was launched in 2002 by Paul Cunningham (CEO) and Steev Wilcox, two PhD graduates from Cambridge University in England. I first wrote about the company for EE Times in 2005, by which time Azuro had 27 employees, $4 million in venture capital, 10 patents pending, and a CTS product called PowerCentric.  In that 2005 article, analyst Gary Smith noted that Azuro "is a lot different than just another clock tree synthesis company." Today, Azuro has over 100 tapeouts.

PowerCentric, Azuro's first product, leveraged new technology for doing clock gating at the physical implementation level. It was basically a better CTS tool that promised skew-balanced clock trees that were 30% smaller and 20% lower in power than existing tools. But Azuro's foremost innovation was Rubix, its clock concurrent optimization tool, now called "ccopt." Rubix combines "useful skew" clock tree synthesis with incremental logic sizing and timing-driven placement, giving the power, performance and area advantages cited above.

Rubix brought about a couple of important technology innovations that are worth noting. First, it used timing based on propagated clocks, rather than the less accurate "ideal" clocks that are typically used for CTS. But a propagated clock model of timing exists only after the clocks have been built. How does Azuro get around this chicken-and-egg issue? The Rubix datasheet says that "a ccopt tool must weave useful clock skew tree synthesis with incremental logic sizing and placement, and the clocks that it builds must be ripped up and re-built many times within a single optimization step. And all this needs to be done within reasonable tool runtime and memory constraints."

Useful skew is another important innovation. Typically, designers try to reduce skew to fit within tight margins. The Azuro technology, however, deliberately uses skew in the arrival time of clock signals at registers to increase chip performance. By skewing clocks properly, certain logic functions on a chip can be given more time to compute a result, while other logic functions can be given less time. As Deokar noted, designs in the past were "blindly built for zero skew, but given the performance requirements of today's GHz designs, useful skew is a huge benefit to designers when implemented effectively and efficiently."

For further information about Azuro technology, see Steve Leibson's recent blog post, which offers an excellent summary of a very detailed whitepaper at the Azuro web site.

What This Means for Encounter Users

The Azuro ccopt technology is available immediately as an add-on upgrade to Encounter Digital Implementation System. What this means, Desharnais said, is that Encounter users "now have access to the lowest power, highest performance end-to-end implementation system that is on the market today." Over time, the Azuro technology will be increasingly integrated with Encounter. Not doing advanced-node, high-speed  embedded core design? Then the present Encounter CTS capability will probably work just fine.

Existing Azuro users will continue to be supported, although if they're not Encounter users they won't get the same level of integration that Cadence will provide with Encounter. Azuro ccopt technology uses standard interfaces and can run with any compliant place and route system.

Desharnais sees the Azuro acquisition as a key milestone in the Cadence EDA360 Silicon Realization strategy, which calls for a deterministic, end-to-end IC implementation flow based on unified intent, abstraction, and convergence. Now the Azuro technology will be folded into such a flow. "A point tool strategy is not a sustainable strategy," Desharnais said. "Azuro recognized that, and they picked what they believed was the biggest opportunity for them to grow."

Richard Goering

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