If you can speed your verification by 6X while finding more bugs, that's a pretty good deal. And that's exactly what happened when Cisco Systems turned to formal verification for a complex statistics block, according to a Design Automation Conference (DAC 2011) paper authored by Oski Technology, Cisco, and Cadence.
I did not attend the paper session, but I conducted the video interview shown below with Vigyan Singhal, CEO of
Oski Technology, the same day at DAC. Oski is a verification services firm that specializes in formal model checking. They use tools including the Cadence Incisive Formal Verifier (IFV) and Incisive Enterprise Verifier (IEV). Oski also provides abstraction models that help formal tools achieve convergence.
In the video interview, Singhal discusses the adoption and acceptance of formal technology, why formal can offer faster verification than simulation, what types of blocks are best suited for formal, what types of blocks are
not suited for formal, and how users can merge coverage results from formal tools and simulation. In particular, Singhal notes that IFV and IEV can generate coverage results with the same meaning as simulation coverage, a development he calls "extremely exciting."
We also talked about the DAC paper, which describes how what was projected to be an 18 month effort with dynamic simulation was cut to 3 months with IFV. The statistics block was exhaustively verified and 26 bugs were found, of which 10 would have been practically impossible to find with simulation, according to the authors.
Formal verification is not as difficult as many might think. "When you apply formal verification, you don't need a PhD, you need good problem solving skills," said Singhal, the only person in Oski who does have a PhD in formal verification. "Once you have the problem solving skills, the bandwidth and the resources, I think you're all set."
If video does not open,