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Video: Open-Silicon CEO Warns of “Exponential Verification Nightmare”

Comments(0)Filed under: DAC, verification, Open-Silicon, Sherwani, IP integration, ChipEstimate.com, video, IP verification, Interlaken, nightmare

The biggest challenge with chip design and IP integration is verification, according to Naveed Sherwani, president and CEO of Open-Silicon - and things aren't getting easier. "I believe that unlike many other industries, we have not developed our verification system in a hierarchical manner, in which chip designs are inherently verifiable," he said. "As a result we find ourselves in an exponential verification nightmare."

Strong words, but Sherwani speaks from the experience of hundreds of IC designs. His company is a fabless semiconductor provider that focuses on ASIC "derivatives" in the networking, telecom, computing, and storage areas. The company works extensively with third-party IP and now offers some of its own silicon-proven IP, including Interlaken Protocol IP listed at the Cadence ChipEstimate.com site.

In a Design Automation Conference video interview, I asked Sherwani about Open-Silicon's "on time or on us" program, in which the company will refund NRE costs if they are unable to meet schedules. We talked about IP quality, and Sherwani insisted that test chips alone do not result in "silicon proven" IP. We also talked about the verification challenge. "I think as an industry we have to commit ourselves to IP reuse in a verifiable manner," he said. On the video, he shares some of his ideas about what needs to be done.

You can access this video on the ChipEstimate.com site or by clicking below.

Richard Goering


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