In May 2011 Cadence announced the acquisition of Altos Design Automation, a provider of ultra-fast characterization tools that model timing, noise, power, and process variations for "foundation" IP (standard cells, I/Os, memories). In this interview Jim McCanny, co-founder and former CEO of Altos, discusses the company's mission and technology, the increasing need for fast and accurate characterization, how fast characterization boosts IP reuse, and how Altos and its customers will benefit from the Cadence acquisition.
Q: Jim, let's start with some background. When was Altos founded and why?
A: We started in 2005, when a couple of our founders wanted to go start a new venture. They asked me for advice on what to work on, and I told them that everyone is working on analysis, DFM [design for manufacturability] and statistical timing, but nobody is putting much attention on how to create the models that support all this. So they went off and started developing ideas to speed up characterization.
The team had prior experience in doing characterization work for noise. We could build libraries in a couple of hours, and the competition was taking weeks or months. We felt that some of the ideas we used to speed up characterization for noise could also be applicable to timing and power. We were also thinking that statistical timing was going to take off and that people were going to need libraries.
Q: What's your role now at Cadence?
A: Today I am senior group director of R&D for the Foundation IP Characterization group at Cadence, which is under the Virtuoso Silicon Realization group. Most of the Altos team came over [to Cadence] and moved into the R&D organization, and I will continue to manage that organization.
Q: Altos was known for fast characterization. What were you characterizing?
A: The main thing that's driven our business is standard cells. In the last 18 months we also had a lot of success with I/Os, from simple I/Os to more complex ones like USB 2.0 and DDR3. Memory is a fairly new business for us. We've had some pretty good success with memories, but we feel that being part of Cadence we'll have a lot more synergy, and we feel [memory characterization] can really flourish under Cadence.
Q: Characterization has been around a long time. What did Altos bring that's new?
A: We came up with a collection of techniques called "inside view" that try to do characterization smartly. First and foremost, we try to understand the circuit we're going to try to characterize. We identify the paths through the circuit, the function of the circuit, and the vectors needed to simulate the circuit. We don't need to exhaustively try all vectors if we know certain vectors are going to be essentially redundant. We recently received a patent for our "inside view" technology.
Additionally, for memory characterization, we added a "dynamic partitioning" technology. Traditionally there are two techniques for characterizing memory. One is to run a fast SPICE simulator, which doesn't scale with the size of the memory and has inaccuracies. Another is to manually cut out critical paths and run a real SPICE simulator. Our approach uses the best of both worlds. It simulates the entire memory once in a fast SPICE simulator to determine the dynamic activity of the circuit. Then we can carve out what's necessary to accurately represent the critical paths, and run a real SPICE simulator.
So we bring a lot more automation, which has two advantages. One is that you can get much better throughput, and another is that we reduce the burden for the end user in setting up the characterization.
Q: What's driving the need for fast IP characterization?
A: There are two major forces, and one is power. Low power design has created the need for more cells in the library and has expanded the number of cell options and library choices. Low power results in a lot more complexity, with the need for state retention flops and level shifters. Another factor is process variation. This means people need more corners to cover the design space. This has also driven the need for SSTA [static statistical timing analysis] models, and while SSTA has not exploded as we expected, there are enough leading edge companies taking an interest that we can differentiate our offering by supporting SSTA.
Q: So we have more cells, more complexity, more corners - all of which slows down characterization, right?
A: Yes. Characterization is very labor intensive and compute intensive. A lot of existing tools are in-house tools built around scripts, with very little intelligence. This is not viable any more. People can spend significant dollars with us and still have a significant savings on their hardware costs and software costs, because they need fewer simulators and don't need a farm of computers for characterization.
Q: What products did Altos develop?
A: The initial product is Liberate, a standard cell and I/O characterization tool. The second product is Variety, which was developed to build SSTA models and now builds OCV (on-chip variation) tables as well. The third product is Liberate MX, for memory characterization. The fourth product is Liberate LV, which takes a library and exercises it in analysis tools like the Encounter Timing System. These tools are still sold and supported.
Q: IP reuse is a key element of the EDA360 vision. How does fast foundation IP characterization help?
A: A lot of people are getting IP from internal or external groups, and quite often they want to re-characterize that IP to a performance or power setting that is more in tune with their application. For example, they may just want to run something at a lower voltage and gain a power savings without hurting their timing. We have an environment that can very quickly and clearly tell design groups if IP will function and perform according to power and noise requirements. The ability to create models in a very efficient and automated way is really fundamental to IP reuse.
Q: How does the acquisition benefit Altos, Altos customers, and Cadence?
A: Altos caught this [characterization] wave and developed technology at the right moment, but the wave is not getting any smaller. People are starting to adopt 28nm, and 20nm is on the horizon. The characterization burden and the number of corners are increasing. The need for our technology is growing very rapidly and it was difficult for Altos to scale to meet the demand. Being part of a bigger organization gives us immediate feet on the street.
Altos customers will get better support, and their risk will be lower. Some customers hesitated to engage with us because we were a small independent entity. Another point is that we can take advantage of synergies between Altos technology and Cadence tools going forward.
As for benefits to Cadence, Altos tools are used by a number of IP providers and foundries, and that's a good strategic fit for some of the initiatives Cadence has in place. It allows Cadence to interact early in process development. The acquisition also gives Cadence an opportunity to sell more simulators into the standard cell and memory characterization market.
Q: Finally, how does Altos technology fit with the EDA360 vision?
A: I think it fits in very nicely - it provides bridges between a number of different worlds. Characterization is a pathway from the transistor-level world to the digital world and the abstract model world. It allows people to design very large SoCs with a lot of IP and thus enables SoC Realization. So I think it's a critical piece. The reason we call it "foundation" IP is that it provides the foundation for SoC implementation.