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ARM ACE Verification IP: Verifying Hardware Cache Coherency

Comments(0)Filed under: Industry Insights, ARM, DAC, Verification IP, VIP, UVM, AMBA, AMBA 4, Cortex-A15, cache memory, interconnect monitor, ACE, cache, cache coherency, multi-processor, ICM

Cache coherency is essential for any processor-based system that uses cache memory. And now, it is moving from software into hardware in multi-processor mobile devices, due to ARM's new AMBA 4 Coherency Extensions (ACE). What does that mean from a verification standpoint? Newly available verification IP (VIP) specifically for the ACE protocol provides an answer.

Primarily aimed at multi-processor ARM Cortex-A15 designs for mobile devices, ACE provides hardware-level cache coherency. Cadence today (June 6, 2011) announced its support for ACE with an AMBA 4 ACE verification solution.

The shift from software to hardware cache coherency is "pretty dramatic and significant," according to Pete Heller, senior product marketing manager for Verification IP and Interconnect at Cadence. Why is it happening? "Software cache concurrency schemes take too many cycles and consume too much power," Pete said. "To gain back those cycles and to reduce power consumption, you need to move that into hardware." This is particularly true in mobile computing applications, where "you need to devote your cycles to making the apps responsive while at the same time avoiding major drains on battery life."

More Processors, More Complexity

As Pete explained, single-processor systems can satisfactorily manage coherency using a software-based approach. However, software approaches aren't efficient enough in multi-processor systems. To increase headroom and optimize performance in these systems, coherency needs to move from software into the hardware itself.

One consequence of hardware cache concurrency is that verification is more complex. Directed testing isn't adequate because the state space is too big - engineers cannot write specific tests for every possible scenario that could occur within the system. Thus, constrained-random stimulus generation is needed, along with functional coverage. It is essential to look for VIP that supports this methodology when performing ACE verification .

A Two-Part Solution

The Cadence ACE VIP solution has two parts, both of which are required. One is the ACE VIP itself, which is used to ensure that each individual processor and memory behaves correctly. This VIP provides constrained-random test generation and functional coverage to verify the operation of masters and slaves. The second part is an Interconnect Monitor (ICM) that monitors the interconnect to ensure that communication between all components is accurate and in compliance with the ACE specification. The graphic below shows how the VIP and ICM work with the device under test (DUT).

The Cadence ACE VIP resulted from a close collaboration with ARM. It works with simulators from Cadence, Mentor Graphics, and Synopsys; supports the UVM and VMM verification methodologies; and works with languages including SystemVerilog and e. It is part of the Cadence VIP Catalog.

The VIP press announcement is available here. For additional information visit the AMBA VIP web page, see Cadence in booth 2237 at DAC in San Diego, or attend the ARM, Cadence and TI Exhibitor Forum on June 7 at DAC.

Richard Goering

 

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