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Q&A: A Closer Look at the Cadence Rapid Prototyping Platform

Comments(0)Filed under: Industry Insights, FPGA, Simulation, EDA360, emulation, prototypes, software, System Development Suite, FPGA prototyping, Rapid Prototyping Platform, prototyping, hardware/software integration, Palladium XP, rapid prototyping, RPP, Jaeger

Cadence entered a new marketplace with the recent introduction of the Rapid Prototyping Platform, an FPGA-based prototyping environment that supports pre-silicon software development and system validation. The Rapid Prototyping Platform is part of the tightly integrated System Development Suite, which also includes virtual prototyping, simulation, and acceleration/emulation.  In this interview Juergen Jaeger, senior product marketing manager at Cadence, talks about the limitations and challenges of FPGA-based prototyping today and discusses some of the capabilities provided by the Rapid Prototyping Platform.

In a previous interview Michał Siwiński of Cadence discussed the hardware/software integration challenges that are addressed by the System Development Suite. A subsequent interview with Steve Brown provided more detail about the Virtual System Platform.

Q: Juergen, how are customers using FPGA-based prototyping today?

A: Most FPGA-based prototype boards are used for pre-silicon software development. Customers also run system-level regressions that take too long in simulation or even emulation. Plus, some customers use FPGA-based prototypes as development kits that are given to end customers, so those customers can do system integration and write drivers or other software. FPGA-based prototyping, however, is not a replacement for emulation and is not typically used for RTL or chip verification.

Most customers today are still using custom boards or in-house boards. However, the number of customers who are purchasing off-the-shelf boards has steadily increased over the past several years.

Q: When customers design their own FPGA prototype boards, what challenges to they run into?

A: There are many challenges. For many companies who develop ASICs and SoCs [systems on chip], building boards and designing with FPGAs is not their core competency. So, they have to fund an additional team of board experts. Then they run into the typical board issues including manufacturing, yield, signal integrity, power, and so on. After the boards are deployed and an error shows up, there is always a question as to whether the error is in the design or on the board itself.

Another issue is that it takes man-months for the development of a board through PCB layout, manufacturing, and board testing. By the time it comes back the design may have changed. There may be so many changes along the way that you have to start all over again.

On the other hand, when you build a board specifically for an SoC or ASIC you can reflect the architecture of the chip and not waste infrastructure on the board.

Q: What challenges arise when customers purchase off-the-shelf FPGA prototype boards?

A: Most vendors who have off-the-shelf FPGA boards have the boards only. They have little or no software that allows you to map the SoC design, so you go to a second vendor to get the [mapping] software. Then you go to an FPGA vendor to get the place and route software. So there is a lot of assembly required. If something goes wrong, it is often difficult to get support.

Q: Why is Cadence entering the FPGA-based prototyping market?

A: We realized that the effort our customers are spending on software development, system integration, and hardware/software co-design and co-verification is constantly increasing. Now more than 50% of the effort is spent on the software side. Traditional EDA tools help a chip get to tapeout, but don't help much with the software that goes with it. We realized this was an area where we could help our customers significantly. Also, FPGA-based prototyping is a very natural way of complementing and enhancing our emulation offering in the Palladium XP Verification Computing Platform.

Q: How does the Rapid Prototyping Platform complement the Palladium XP?

A: Because of its price point, you can deploy FPGA-based prototypes to the whole software development group - you could have 20, 30, 50 rapid prototyping systems. The Rapid Prototyping Platform offers an order of magnitude faster performance than the Palladium XP, so you can run software on it more easily. Also it's a much less complex system than the Palladium XP. The software developer can simply switch it on, connect a software debugger to it, and run it like an ASIC.

Rapid Prototyping Platform

On the other hand, the Palladium XP offers a quick path to implementation for an ASIC. For an FPGA-based prototyping system to work, the ASIC has to be in a stable enough state to execute software on it. Palladium helps you get the ASIC to that stable state. It has superior debug capabilities and very fast compiles.

Q: What is the connection between the Rapid Prototyping Platform and the Palladium XP Verification Computing Platform?

A: We use the same compile engine, which means we have identical language coverage. The constraints, memory definitions, and clock definitions are identical, which helps you port your design over very quickly. Palladium also has SpeedBridge rate adapters for protocols like PCI Express. The SpeedBridge adapters are shared and are compatible with the Rapid Prototyping Platform. Finally, when a test fails in FPGA-based prototyping, the user can go back to the Palladium and use the advanced debug capabilities available there.

Q: Does the Rapid Prototyping Platform speed bring-up times compared to existing FPGA-based prototyping systems? By how much, and why?

A: The typical bring-up time for FPGA prototyping systems is between 3 and 6 months - and that's for off-the-shelf boards. If we're talking about full-custom boards you can add another 3 months. With the Rapid Prototyping Platform, however, we are going through an intermediate stage with the Palladium. We are able to cut that [bring-up] time to 2 to 4 weeks. That allows you to start using the prototyping system much earlier, which means software developers are getting a head start.

Several things allow the time to be cut. For one, we are reusing a lot of work that was done during RTL emulation already. We also have a fully automatic partitioning flow in the Rapid Prototyping Platform. And because we are using technology from the emulation system we have very fast compiles, and we even include the FPGA place and route software.

Q: What hardware is included with the Rapid Prototyping Platform?

A: There are four hardware configurations. It starts with a simple two-FPGA board with a high number of I/Os, providing roughly 10M ASIC gates capacity. The three other configurations use a different board that has standard interfaces like Gigabit Ethernet, USB and PCI Express. This board can have two, four, or six FPGAs, going up to 30M gates capacity. The FPGAs are currently Altera Stratix IV 820 devices, the largest capacity FPGAs in the market.

Q: What debug capabilities are provided?

A: We have debug capabilities directly built into the system. Users can specify signals they want to observe during run times; you basically compile a soft logic analyzer into the FPGAs. We capture the data during run time and we create a VCD waveform file. The second option is through what is called Mictor connectors - these allow you to connect an external logic analyzer. A third option, because we create a Palladium-compatible model, is to rerun the model on Palladium and use all the advanced debug capabilities in Palladium.

Q: How does the Rapid Prototyping Platform help realize the EDA360 vision?

A: The Rapid Prototyping Platform is expanding the usage of our solutions more into the system development space. It provides an additional platform that allows system integration and early software development. With the Virtual System Platform and the Verification Computing Platform, our offerings provide a very comprehensive environment for the industry that reflects the change to an application-driven, software-centric, and software differentiated landscape.

Richard Goering



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