The EDA360 vision, articulated by Cadence one year ago, is not about one company - it's a vision for an entire industry. As such, EDA360 depends on a collaborative ecosystem with many players, including other EDA vendors, silicon IP providers, foundries, design services companies, and many others.
Standards represent the "glue" that holds this ecosystem together. Standard languages and formats are necessary to convey information between providers, and between suppliers and customers. Standard protocols are essential for chip architecture and design. Standards let all players focus on their unique "value add" and stop re-inventing the wheel with non-differentiating technology.
In a recent blog post Steve Schulz, Silicon Integration Initiative (Si2) president, discussed EDA360 from a standards perspective. He described the market shift represented by EDA360 and wrote about his "vision of well-timed standards playing an increasing role to open up new market opportunities, allowing the industry to hit ‘economic critical mass' by lowering cost and improving efficiency."
To add to the discussion, I recently talked to Stan Krolikoski, group director of standards at Cadence, and Ken Potts, product marketing director, who works with Si2 standards. We looked at the standards that underlie System Realization, SoC Realization, and Silicon Realization. Some perspectives on standards follow.
System Realization - SystemC Enables Virtual Prototyping
System Realization is described in the EDA360 vision paper as the creation of hardware/software systems ready for applications development and deployment. Cadence took a big step towards System Realization May 3 with the announcement of the System Development Suite, a set of four integrated hardware/software development platforms. While many previous development platforms have used proprietary formats, this suite is solidly based on industry standards such as IEEE 1666 SystemC.
One platform in the suite is the Virtual System Platform, which provides pre-RTL software development on SystemC transaction-level models based on the Open SystemC Initiative (OSCI) TLM 2.0 standard. The Virtual System Platform uses an extended version of the Cadence Incisive SystemC simulation and debugging environment, providing a close link to RTL simulation and acceleration and a common debug interface. A TLM model generation utility takes in IP-XACT descriptions and does most of the work required to produce SystemC TLM models. This utility can also provide a TLM "wrapper" for legacy C/C++ models.
SoC Realization - Describing Silicon IP
SoC Realization is the creation of an individual SoC, and IP-XACT will play a key role here. Developed by the SPIRIT Consortium before it merged into Accellera, this standard describes a meta-data documentation format, based on an XML schema, for packaging, integrating, and re-using silicon IP. It allows the transfer of IP and IP information between companies while protecting proprietary data.
Of course, SoC integration is dependent on a number of "non EDA" standards, including interface standards such as PCI Express and Gigabit Ethernet, and memory standards such as DDR3 and DDR4. With third-party design IP offered by providers including Cadence, designers can implement standard protocols without having to design non-differentiating hardware.
Silicon Realization - Expressing Intent
Many standards underlie Silicon Integration, which is the creation of analog, digital or mixed-signal silicon IP. The three requirements of Silicon Integration are unified design intent, appropriate use of abstraction, and convergence into a manufacturable solution. None of these attributes are possible without standards.
The OpenAccess database, now used by a number of vendors and design platforms, makes it easier to pass constraint information (design intent) between analog and digital designers - or between tools from different vendors. The Common Power Format (CPF) makes it possible to represent power intent. The Si2 OpenPDK effort seeks to establish a single data source that EDA vendors can compile into their unique process design kits, giving the manufacturing community a common language to describe their processes.
The Accellera Unified Verification Methodology (UVM) standard will certainly help with Silicon Realization, but it doesn't stop there. Endorsed by all major EDA vendors, UVM will provide interoperability among verification IP (VIP) and verification tools. UVM is initially aimed at SystemVerilog, but efforts are being discussed to extend UVM to SystemC and to the e language. The result, said Stan Krolikoski, would be "a universal verification methodology that spans the three Realization levels and ties a lot of things together."
More Work Required
More remains to be done. For example, OSCI is continuing to work on a synthesizable SystemC subset. Stan also sees a need for "interface standards between SystemC hardware and the embedded software world," and noted that OSCI has discussed this need but hasn't acted yet. "This is something that needs to be pushed," he said.
But we also have to remember how much has been accomplished with standards in the past few years. With standards like OpenAccess, UVM, and SystemC, the EDA360 "Realizations" are taking root today within a standards-based ecosystem, just as the original vision predicted.