The 48th Design Automation Conference (DAC) is just a little over one month away, and Cadence will have a substantial presence on the exhibit floor, in panel sessions, and in co-located workshops. Of course, the famous Denali Party is a highlight, and it is on! A new Cadence DAC microsite located here provides an overview of Cadence activity at DAC, including the Denali Party and the "I Love DAC" campaign. DAC is scheduled for June 5-9 in San Diego, California.
Let's start with an event that many people have been waiting for -- the Denali Party, which has been the social event of the conference for the past several years. Now called the Denali Party by Cadence, the party will take place Tuesday, June 7, at Fluxx, a nightclub and private event venue located in San Diego's historic Gaslamp Quarter. The party runs from 8:00 pm to 1:00 am.
The party will feature the EDA360's Got Talent competition on the Fluxx main stage. The microsite has instructions for entering the competition as well as a form for reserving your party ticket. You must pick up your wristband at the Cadence booth (#2237) before noon on Tuesday June 7.
I Love DAC
Atrenta, Cadence, and Springsoft are continuing the I Love DAC promotion in 2011. All three companies are sponsoring exhibition hall passes for non-exhibiting companies. Registration is available at the Cadence DAC microsite mentioned above.
On the Exhibit Floor
The Cadence booth is #2237. The booth will feature an EDA360 Theater with a variety of live presentations from customers and partners. The ChipEstimate.com booth is #1731. Here you can learn about the latest in silicon IP from presentations on the IP Talks! stage.
DAC 2011 includes 29 panels, including "Pavilion" panels on the show floor and panels that are part of the regular technical program. Here are a few with Cadence participation.
Session 13 - Cloud Computing and EDA Forecast: Sunny Skies or Storm Clouds Ahead?
Time: 4:00 PM - 6:00 PM, Tuesday, June 7
Cloud computing is the buzzword today in the software industry. So how and when will cloud computing affect EDA and IC design? Immediate concerns looming on the horizon are security, the transfer of large data sets, and licensing models. This panel, representing a broad set of design and EDA constituents, will examine cloud computing's many implications for the IC design ecosystem.
John Bruggeman, Cadence CMO, will participate in this panel along with speakers from Synopsys, GLOBALFOUNDRIES, IBM, and Madrona Venture Group.
Pavilion Panel - Stop That Thief! IP in Global Markets
Time: 1:00 PM - 1:45 PM, Wednesday, June 8
IP reuse is the de-facto model for SOC development. Emerging markets are increasingly becoming both consumers and suppliers of design IP. Panelists involved in the development and integration of IP discuss the technical, business, and legal aspects of cross-regional IP sourcing. What can the IP ecosystem do to promote business integrity worldwide?
Adam Traidman of Cadence (ChipEstimate.com) will moderate a panel with speakers from GLOBALFOUNDRIES, IDT, and attorney Jonathan Kaplan.
Session 25 - Software-Hardware Verification Battle: Prototyping vs. Emulation
Time: 2:00 PM - 3:30 PM, Wednesday, June 8
Some say prototyping is essential -- but that could be by virtual prototype or by FPGA. Others say emulation is the way to go. Who is right? Experts from academia and the industry will wrestle with the question to determine the best way to success.
Chris Tice of Cadence will appear on a panel with speakers from Stanford, IBM, Synopsys, Intel, and Qualcomm.
In recent years DAC has added a number of co-located workshops and events. The following workshops include Cadence speakers:
DAC Workshop on Intra and Inter-Vehicle Networking: Past, Present, and Future
Time: 9:00 AM - 5:00 PM, Sunday, June 5
This workshop focuses on the past, present, and potential future landscape of intra and inter-vehicle communication technologies. Arthur Marris of Cadence is a speaker. Alberto Sangiovanni-Vincentelli, professor at U.C. Berkeley and Cadence board member, is chair.
DAC Workshop on Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems
Time: 10:00 AM - 1:00 PM, Sunday, June 5
This workshop will provide an example-based overview of UVM to chip and SOC design and verification engineers. Stan Krolikoski of Cadence is the organizer and Sharon Rosenberg of Cadence is a speaker.
Synergies in IC Design: PDK and DFM Standards Working Together
Time: 8:30 AM - 12:30 PM, Monday, June 6
This co-located event is organized by Si2, and considers standardized industry practices for design for manufacturability (DFM) and process design kits (PDKs). Barry Nelson of Cadence is a speaker. Other speakers are from Mentor Graphics, STMicroelectronics, Texas Instruments, IBM, and LSI Logic.
If you haven't yet registered for DAC, there's no better time than the present. Further information is located at http://www.dac.com/.