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EDA360 Beyond the Chip – Package, Board, and Product Creation

Comments(0)Filed under: Industry Insights, Allegro, Co-Design, PCB, EDA360, system realization, SoC Realization, Silicon Realization, PDN, XML, board, package, MCAD, packaging, DDR3, Allegro 16.5, ProStep

The EDA360 vision, articulated by Cadence one year ago this week, calls for an expanded view of EDA that supports complete hardware/software systems ready for applications deployment. Most of the discussion during the first year focused on silicon and embedded software. A Cadence Allegro 16.5 announcement today (April 25) illustrates how EDA360 also encompasses package and board design.

It seems obvious, as soon as you think about it, that a "complete system" would have to include packages, one or more boards, and some kind of enclosure. If you doubt that, gather up all the silicon components that will go into a cell phone before they go into packages or onto boards, and try to make a call.

Further, as silicon nodes shrink, there are more and more interdependencies between chips, packages, and boards, and more requirements for co-optimization. Keith Felton, product management group director for PCB and IC packaging, puts it this way: "just being able to design a chip is not enough. You have to be sure you can design the chip in the context of the system so you know your chip will work when you bring it into the marketplace."

The Allegro IC packaging and PCB design tools are, in fact, a vital part of the EDA360 vision, according to Dave Desharnais, product management group director for Silicon Realization. He noted that Allegro is a great example of Cadence product line that was developed as a bridge connecting all three EDA360 "Realizations" -- System Realization, SoC Realization, and Silicon Realization -and that it extends the vision all the way to product creation. "Allegro uniquely touches everything we do today from an EDA360 perspective," he said.

Here's how, with a look at each "Realization" in turn. 


Silicon Realization and Distributed Co-Design

Silicon Realization is defined as the creation of analog, digital or mixed-signal silicon IP, or discrete chips without processors. It is enabled by a holistic design flow that meets three requirements - unified intent, abstraction, and convergence. But silicon cannot be designed in isolation from the package it will go into, especially when cost, form factor, and power are concerns. Thus, IC/package co-design is an essential part of EDA360 Silicon Realization.

The Allegro 16.5 release provides a new "distributed co-design" capability. It complements the "concurrent" co-design offered in previous Allegro versions, where chip and package are optimized concurrently in a synchronized fashion. That may not work well with geographically distributed teams, especially if data must go outside the company firewall to be transferred between teams. With distributed co-design, a high-level XML definition of a chip and package is exchanged, rather than the data for the entire chip or package.

This XML definition is an excellent example of abstraction, one of the three requirements of Silicon Realization. Design intent is represented by pinouts, parasitics, netlists, and other information exchanged between the package and board environments, and it must be "unified" so that signal names are consistent. Convergence occurs as a "package-optimized" chip is successfully taped out. The result: a system that meets demands for performance, low power, cost, and form factor at time when the number of chip I/Os is greatly increasing.

SoC Realization and Board Enabled IP

SoC Realization is the creation of a single system-on-chip. SoCs include one or more processors, a memory subsystem, and various interfaces. They're comprised of internally developed and externally acquired IP blocks. But this IP must still go into packages and onto boards.

If you want to comply with the DDR3 spec, for example, it's not just the silicon IP that needs to comply; it's the overall system. That means the package and board have to be considered. The Cadence DDR3 design IP now comes with a Design-In Kit that ensures signals are going to work across the package and board. The kit includes a controller I/O and IC package model, a timing derating model, a connector model, a memory model, topologies, constraints, and documentation.

System Realization and Product Creation

System Realization is the creation of a hardware/software platform ready for applications deployment. OEMs want that these days because their main differentiation is increasingly in their software "apps." Most OEMs are going to want a platform that not only comes with packages and boards, but is optimized for performance, power, signal integrity and cost across the chips, packages, and boards.

Most of the talk about low power design is strictly at the silicon level. However, as Keith Felton noted, "the power supply connects through the board up through the package. If you do a phenomenal low power chip implementation, and put it in a poor package or on a poor board, you've just wasted your time." To help avoid this problem, the Power Delivery Network in Allegro 16.5 uses full-wave field solver technology to analyze power problems that show up at the board level.

There are several other examples of how Allegro 16.5 supports System Realization, including:

  • A Design Authoring Team option that allows multiple designers to work on the same design in a structured manner
  • Incremental data exchange with mechanical CAD (MCAD) systems through the new ProStep EDMD Schema standard
  • Broader support for embedded packaged components in inner PCB layers
  • A new PCB interconnect design planning technology
  • An ability to track project and business analytics for MCAD and EDA

In summary, I think it's clear that EDA360 is not just about silicon and software. Adding in the package and board, along with links to mechanical CAD, makes it a much more complete and compelling vision - and we're talking about something that is available today.

Richard Goering



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