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User View: Challenges and Solutions for Memory IP Development

Comments(0)Filed under: Industry Insights, Virtuoso, Analog, OpenAccess, memory, custom, custom/analog, memory IP, layout, OTP, Design Navigator, Gusto, Virtuoso 16.1, Kilopass, NVM

Developing memory IP isn't easy - it's repetitive full-custom work that requires verification of many possible configurations. While full automation isn't possible, there are ways in which design tools and methodologies can make the task much easier. A recent conversation with engineers at Kilopass Technology illustrated some of the challenges they face, and ways in which they're easing the flow using several advanced features in the Cadence Virtuoso IC 6.1 release.

Kilopass develops one-time programmable (OTP) non-volatile memory (NVM) intellectual property blocks. The company sells hard IP to IDMs and fabless semiconductor companies, who integrate the IP into systems-on-chip. Kilopass' latest product line is Gusto, offering up to 4 Mbits memory.

I recently talked with Bill Ip, principal engineer, and Shiang-Mei Heh, layout manager, about memory IP design and the work they're doing at Kilopass.

Challenges of OTP Memory IP

Kilopass provides IP for process nodes ranging from 180nm to 40nm, and 28nm is under development. All the usual challenges of small geometries apply - design for manufacturability (DFM), design rules, lithography. Yield enhancement is an important part of memory qualification, and it's difficult to predict yield loss for a new process until silicon comes back from test runs. "It's not a straight CMOS transistor," Heh said. "We cannot use a CMOS calculation to get to the [yield] answers."

With memory sizes that range from 1 Kbits to 4 Mbits, designers must create models for many different configurations. As a result, Ip said, it takes a long time to get through the verification process. Each configuration needs to be qualified for at least five corners. If anything doesn't work the designers have to go back and modify the layout, resulting in long cycle times.

While most Kilopass customers employ a top-down approach to build their SoCs, the development work at Kilopass is bottoms up. Designers start with a "one and a half" transistor bit cell and then replicate it horizontally and vertically to build more complex arrays. "We have to determine transistor dimensions and spacing between poly to get it right, and at new process nodes everything is totally new," Heh said. Designers end up trying many different memory sizes, and then they have to run test vehicles to see what works.

Bringing in Automation

Ip said that 80 to 90 percent of the Kilopass IP design work is purely handcrafted, but there are some control logic blocks that go through a digital place and route process. These are usually shipped to outside contractors who may use Cadence or Synopsys tools for this task. One Virtuoso IC 6.1 feature that's very helpful, Ip said, is its use of the OpenAccess database. "They [contractors] give us the data and we can do our edit here in Virtuoso. If we have an ECO in a control block we can ship it back to them and they can work on the same database," Ip said.

Most device designers don't have layout expertise, Ip said, but there's a feature in Virtuoso IC 6.1, called Design Navigator, that's very helpful to them. This is a feature that lets designers open a layout they're not familiar with and identify cells with a given dimension.

Virtuoso IC 6.1 can also help automate repetitive tasks and is useful in building memory arrays, Heh noted, because engineers build a memory cell and then repeat it. "You can generate the same layout, but in different configurations," Ip added. He also noted that the circuit designer can do a "representative layout" that helps determine the placement of critical blocks.

Another Virtuoso IC 6.1 feature allows Kilopass circuit designers to place constraints in the netlist, thus preserving the designer's intent in a way that's understandable for the layout engineers. "They can put in parameters and comments and we can see them on the screen," Heh said.

Analog "Automation" is Possible

Ip observed that Virtuoso IC 6.1 is rich in features and has "more than we can utilize." He said he'd like to take a training class "so we could learn about some of the hidden features we're not using right now."

Is custom/analog "automation" an oxymoron? Not necessarily, Ip said. "I think layout automation can really help analog designers, especially in tight spots or with different aspect ratios," he said. "If the tool is easier to use, designers will contribute more." On the layout side, he'd like to be able to use an "if-else" kind of capability to change width and length and run extraction and simulation. "I'd like to get all those things in one pass," he said.

Richard Goering


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