Home > Community > Blogs > Industry Insights > arm keynote some inconvenient truths about low power design
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the Industry Insights blog (individual posts).


* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

ARM Keynote: Some Inconvenient Truths About Low-Power Design

Comments(0)Filed under: Industry Insights, ARM, low power, low-power design, low-power, Power, Electronic Design Processes, EDP, models, state retention, SRAM, Aitken, power gating, DFVS, IR drop

While there have been many advances in low-power IC design, it still involves tough choices and poses difficult questions, according to Rob Aitken, R&D fellow at ARM. Aitken talked about the myths and realities of low-power design in a keynote speech at the recent IEEE Electronic Design Processes (EDP) workshop.

On the surface, it's getting simpler, because the various low-power design techniques are "coalescing into a few fairly straightforward solutions," Aitken said. For example, designers have turned away from fine-grained power gating, and although everyone requests body biasing in cell libraries nobody seems to use it.

But there are still a number of harsh realities, and the first of these is that you can't just talk about "low power" without being more specific. "Go ask a fab about low power and you'll wind up with a low leakage process, and if you build something in that process you'll find it has higher dynamic power," Aitken said. "The first step in any low-power system is to determine which is more important - leakage or dynamic power - and then work with that."

Here are some other points that emerged from the keynote:

Power gating raises tough choices. You have to decide where to put power gates, whether to use header or footer switches, and how to size the gates. The bigger you make them, the safer your switch network is, but the worse your leakage is in sleep mode. Adding state retention makes things more complex. "Power gates are easy. Retention flip-flops are tough to design," Aitken said.

In-rush current can kill your network. "Sudden in-rush current can really do a number when you charge stuff that's been discharged," Aitken said. Designers have used various strategies to avoid problems, but "the only thing you're assured of is that if you don't think about this, you can be pretty much assured your chip won't work."

State retention approaches involve tradeoffs. If you store the state in flash or DRAM, there will be minimal leakage during sleep states, but it will take some time to turn things back on. If you use retention registers to hold the state, it comes back up quickly, but leakage during sleep state is higher. The choice depends on the application - will the user be shutting down for a week or a minute?

The tortoise versus the hare. Open question: is it better to go with a high-performance design that runs fast and then sleeps, or to use a "slow and steady" approach that consumes less energy as it goes along?

Power is really a "system thing." It's useless to invent a solution at the hardware level that the operating system can't access, Aitken noted. "The question of power goes all the way from the OS down to the process technology."

Foundry modeling is not necessarily accurate. "Models are based on bizarre statistics at a very low level," Aitken said. He spoke of looking at a leakage model from an unnamed foundry and finding a constant assigned to 10-12, with the comment that "if this doesn't work, try 10-15." In another case, a foundry acknowledged that its static current number was a "target" that none of its silicon had actually attained. Aitken noted that power models are not based on the CV2f power equation that many designers would expect, but are automatically generated by TCAD software and hand-tweaked later.

Library characterization may be inaccurate, too. There are different ways to measure delay, Aitken noted, and none are technically wrong but they'll produce different results. Libraries "pretend" that a NAND gate will behave the same way no matter where it's placed, but it will actually behave differently depending on what capacitances are nearby.

The IR drop paradox. If you use high Vt devices to create a low power design, the net result is longer switching times, in which case IR drop may create crowbar current. "Paradoxically, when you're trying to reduce power you can actually increase it."

Minimum Vdd and SRAM - a bad combination. When you lower Vdd, "SRAM becomes the first thing to break," Aitken said. That's because it's trying to do three competing things - reading from a cell, writing to a cell, and retaining a value in a cell.

On the plus side, Aitken said, dynamic frequency and voltage scaling (DFVS) has moved to the mainstream, standardization has helped a lot, good IP is available, and there have been "big improvements in low-power tools and flows." What's next is "adaptive solutions" - but that's just an intriguing bullet item on Aitken's last slide. Another talk, for another time.

Richard Goering




Leave a Comment

E-mail (will not be published)
 I have read and agree to the Terms of use and Community Guidelines.
Community Guidelines
The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.