System-on-chip (SoC) design teams have learned they can be much more productive by acquiring processor and interface IP. But most teams still build their own memory and storage controllers - a task that is becoming more difficult, and returning fewer benefits, as complexity grows. Memory and storage management is a new frontier for IP, and it's front and center in the emerging Cadence SoC Realization strategy.
Cadence this week (April 11) is announcing the first DDR4 IP solution, including controller IP, soft and hard PHY IP, memory models, verification IP, and tools and methodologies. Along with that announcement, Cadence is further detailing its SoC Realization strategy. A key tenet of the EDA360 vision outlined last year, SoC Realization is about the creation of individual SoCs, and IP integration is a central part of it.
SoCs require the integration of IP from three primary categories: processors, interfaces, and memory. The Cadence strategy is as follows:
- Collaborate with companies such as ARM in processor IP. No need to re-invent the wheel here.
- Focus on high-performance, high-value interface IP, such as PCI Express Gen3, as well as 10/40 Gigabit Ethernet.
- Leverage years of technology development at Denali and within Cadence Services to provide a broad suite of memory and storage IP in parallel with industry standards, along with a comprehensive integration environment. Examples are this week's DDR4 announcement and last week's wide I/O memory announcement. (In general, "memory" refers to DRAM and "storage" refers to NAND flash).
The Cadence SoC Realization strategy has other elements, including design services and chip planning tools, but the rest of this post will focus on memory and storage IP.
Why Memory and Storage Controllers are Home Grown
So why are so many design teams, who otherwise take advantage of third-party IP, still building their own memory and storage controllers? "Memory has been something that people hold very close to their hearts because their designs are very dependent on how the traffic moves around," said Neil Hand, group marketing director at Cadence. "It touches every part of the chip. It's been viewed historically as relatively simple. And you couldn't trust someone else to do it for you, because if you got it wrong, the chip didn't work at all."
But times are changing, and complexity has dramatically increased. As Marc Greenberg, product marketing director at Cadence, explained it, the DRAMs themselves are getting more complex. Moving to any DDR controller, even DDR1, is a big step up in complexity compared to earlier technologies, and each successive generation of DDR adds to the challenge. There are more and more timing issues, and the scheduling has to be right to get good performance. NAND flash is growing more complex as well and is posing problems in such areas as memory access and error correction.
And then there's the SoCs themselves. An increasing number of SoCs have multiple processors that are trying to access one main memory. Today's SoCs could have CPUs, a graphics unit, a network processing unit, a DSP, a video processor, and more. CPUs may be running different tasks and have different bandwidth needs, priorities, and power states.
With the added complexity, building a memory controller is no longer a simple task. According to Marc, building a "really basic memory controller" will probably take about six engineer-months. The kind of high-quality memory controller that most SoCs will actually need will take much longer. Time is money, so this has a very direct cost implication. Buying a faster memory speed grade to make up for a slow controller costs money too.
Moreover, it's not just building the IP that must be considered - it's also support and maintenance. These will be ongoing burdens for the do-it-yourself approach. And how flexible is that in-house memory controller? If you change memory vendors, or swap in different DIMMs, will it still work? Probably not, unless it's designed up front to support a large number of memory devices.
"With newer generations of DRAM," Marc said, "I think people are finally realizing that it's a challenging enough design that it's worthwhile to look outside one's own organization." Designing your own memory or storage controller IP doesn't differentiate your chip, he noted. Using a high-quality, off-the-shelf controller really does differentiate the chip when it comes to performance.
What makes memory or storage controller IP "high quality?" What overcomes the concern about "trust" that Neil mentioned above?
One factor is longevity. Denali supported DDR for ten years and the IP is licensed in over 260 designs. Denali also had five years of experience with NAND flash controllers. The memory and storage controllers support thousands of possible memory configurations.
Another factor is breadth. As noted in the on-line product description, Cadence memory and storage controller IP typically comes with a standards-compliant controller, hard and soft PHY, verification IP, memory models, and "design-in kit" for silicon/board/package co-design.
Neil said that memory and storage controller IP is "a market that's ready to explode in the same way that interface IP has. But memory requires a more disciplined approach because it touches everything in the system architecture." That's the challenge, and the promise, of the Cadence SoC Realization strategy.