The 3D IC supply chain ecosystem is just beginning to emerge, with roles that are currently unclear. So what happens when you bring together representatives from an outsourced assembly and test (OSAT) provider, memory maker, foundry, EDA vendor (Cadence), and a customer? The result: differing perspectives, and some challenging questions about business models and standards.
This discussion occurred March 31 at a 3D IC Ecosystem panel at the Global Semiconductor Alliance (GSA) Memory Conference. The panel was moderated by Matt Nowak, senior director of engineering at Qualcomm. Panelists included:
- Bill Chen, senior technical advisor, ASE Group (OSAT)
- Kyowon Jim, vice president, product planning, Hynix Semiconductor (memory)
- Paul Kempf, vice president, silicon, Research in Motion (customer)
- Suk Lee, director, design infrastructure marketing division, TSMC (foundry)
- Dave Noice, fellow, Cadence
Most of the one-day conference was devoted to 3D ICs with through-silicon vias (TSVs), and registration filled early, giving an indication that 3D ICs are a hot topic right now. This panel was well-attended and the questions kept coming right up to the end. Here is a brief account of what the panelists had to say, followed by some of the questions that were asked.
OSAT View: Like Running a Deli
"Everyone says 3D is the best thing since sliced bread, so we must close the distance between the bread maker, the deli counter, and the sandwich served on the kitchen table," Chen said. "We [OSATs] are the people behind the deli counter." The problem with 3D ICs, he noted, is that "each customer will be asking for something different."
Since TSV wafers will be coming out very soon, OSATs must be ready with cost-effective, high-yielding solutions, Chen said. He noted that ASE has been doing internal development in 3D ICs since 2007, with efforts in four areas: 3D IC package assembly, silicon interposers (which are built in house), 3D MEMS and sensor assemblies, and heterogeneous integration.
Memory View: It's About Capability, Not Cost
3D ICs are sometimes presented as a way of saving costs, but Jim doesn't see it that way. In the memory industry, he said, "TSVs are not about reducing costs. It's about overcoming some technological challenges we see today," he said.
In fact, Jim said that a cost increase is "inevitable" with TSV technology, due to additional process steps, a die size penalty, and lower yields. So why do it? He noted that the computer, mobile, and graphics markets are demanding high bandwidths, low power and higher capacity. "We cannot supply all these demands with conventional memory technology," he said.
Jim said that Hynix will provide TSV solutions for high-performance and graphics in 2013, and will follow up with other applications, including mobile markets, in 2014. But he has some concerns about the ecosystem. "What if there's a failure after we assemble DRAM with an SoC [system on chip]? Who will be analyzing these failures? How do we deliver known-good die to an assembler? These problems need workarounds."
Customer View: Need Bandwidth, But Keep Stack Low!
Mobile devices need "full system memory bandwidth" that does not need to be partitioned, and is available to all the major subsystems in an SoC, Kempf said. This calls for much higher memory bandwidths, along with low power requirements. That's what is driving RIM's interest in 3D ICs.
Kempf sounded a caution, however: watch the height. "We keep seeing these wonderful pictures of [die] stacks that don't work for us. We need 1.2mm or less to build the kinds of devices people want in the future," he said.
Kempf is concerned about 3D IC standards, because he wants to work with multiple providers. He also has questions about the supply chain. "Who owns the problems, who owns the stack, how do you solve reliability issues, who does failure analysis? These are all things we'll have to deal with."
Foundry View: Look to Silicon Interposers
By providing a silicon layer that can link side-by-side die in one package, silicon interposers represent a step towards true 3D die stacks. That's where Lee sees opportunities today. He noted that silicon interposers fill a "gap" between the high densities provided by on-chip integration, and the lower densities that come from separately packaged ICs on a board. In addition to increasing density, silicon interposers reduce parasitic load and reduce the overall form factor. The silicon interposer "is decoupled from the technology node and is very straightforward to manufacture," he said.
EDA View: Some Assembly is Needed
Noice talked about some of the design tool requirements for 3D ICs. He noted that Cadence started to develop needed capabilities three or four years ago, looking first at how to describe die stacks. Then Cadence engineers developed floorplanning for 3D ICs, providing the "care abouts" that designers need when they're working on a given die in a stack. Placement, routing, analysis, and optimization tools also needed extensions to handle stacked die. (For further information about the Cadence 3D IC/TSV methodology, see my previous blog post.)
Noice noted that Cadence worked closely with foundries, OSATs, and designers, asking designers "what methodology they want to use and what's most important to them." This helped identify what portions of the flow most needed automation. Today, he noted, Cadence has multiple 3D IC tapeouts representing different types of 3D ICs.
Representative Questions and Answers
Q: Who will own liability for failures, and do the failure analysis work?
Panel responses showed this question is still up in the air. It's especially complicated for interfaces between die.
Q: What business model can be articulated for stacked die?
Liability is the sticky part. One business model question is who is responsible for the interface between die. The business model will evolve in 3 or 4 different ways. That's been true for OSATs - different OSATs have different business models.
Q: What needs to be standardized, and where are the gaps today?
Silicon interposer standards are lacking. A wide I/O memory (see my recent post for more information on this) electrical specification is needed, along with a physical standard to help manage interfaces. Nomenclature is inconsistent, with different companies using terms in different ways.
Q: Is there value in driving a standard in via sizes and micro-bump pitches?
This is tied to the process, so a standard in this area is hard to envision. The JEDEC standard for wide I/O memory does include pitches and locations for balls, but not pinouts.
Q: Are standards too restrictive?
Standards in the physical layer are like IC design rules - they will evolve. For concerns like TSV keep-out areas, you can describe the numbers in a standard way, but the numbers will vary.
It's about time that somebody got representatives of the major 3D IC supply chain ecosystem companies into the same room. The discussion showed that much has been done, but a lot of work remains to be done in order to bring 3D ICs into the design mainstream. This panel discussion was part of that work.