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Wide I/O Memory and 3D ICs – A New Dimension for Mobile Devices

Comments(0)Filed under: Industry Insights, IP, 3D, TSV, memory, DRAM, 3DIC, 3D IC, 3D-IC, memory models, JEDEC, Greenberg, Hand, PHY, memory controller, memory IP, wide i/o

There's a lot of excitement about 3D ICs with through-silicon vias (TSVs), and one reason is that stacked die can provide very fast memory access. That's why wide I/O is emerging as a significant new direction for 3D ICs - and why the March 28 Cadence announcement of the first wide I/O memory controller IP may help spur the coming era of 3D integration.

Wide I/O memory is a new DRAM technology and an emerging JEDEC standard that calls for a 512-bit wide interface and 12.8GB/second bandwidth. In addition to high bandwidth, it promises low power consumption. It will initially target the mobile consumer marketplace, where space is at a premium, performance and power demands are stringent, and there is already a movement toward 3D ICs.

While wide I/O does not technically require 3D ICs with TSVs, that's what it is really aimed at, said Marc Greenberg, product marketing director at Cadence. "Wide I/O is really a TSV technology," he said. "There is really no other practical way you could achieve a 512-bit interface to DRAM in a mobile device." Indeed, you would not want to route 512 signal lines on a printed circuit board, and trying to implement wide I/O with wire bonding would require a lot of extra wiring. However, in addition to stacked die configurations, wide I/O memory could be used in silicon interposer implementations with side-by-side die.

Designing for Wide I/O DRAM

A wide I/O memory controller requires wide I/O DRAM, which is not yet available in volume production. But it's on its way, and early designs are in progress. As reported in Steve Leibson's EDA360 Insider Blog, Samsung in February introduced a 1 Gbit wide I/O DRAM that uses micro-bumps to connect its 512 data lines. And Hynix Semiconductor joined a Sematech 3D Interconnect program that has a stated goal of driving the adoption of wide I/O DRAM.

Marc noted that memory systems need to be architected to take advantage of wide I/O. Since the cost per pin is high, it is advisable to multiplex control and address for DRAM banks onto as few pins as possible. But the cost per connection between memory and processor is low, which makes it possible to have multiple control paths between the applications processor and the DRAM. "We can set up simultaneous transactions happening within the DRAM," he said.

While apples-to-apples comparisons are difficult, Marc said there's an expectation that wide I/O will consume less power than LPDDR and other types of memory controllers. "There is certainly less capacitance per pin, because all you've got between the applications processor and the DRAM is a tiny bit of metal and a via. Each pin is driving less of a load and is driving it at a lower frequency."

In most 3D stacks, Marc said, the bottom chip will be the applications processor and will have a flip-chip connection to the substrate. The DRAM will be mounted on top of it and will be connected using TSVs. Alternatively, for thermal-sensitive designs, the DRAM chip may be located on the bottom because the applications processor generates more heat.

Part of the Ecosystem

Neil Hand, group marketing director at Cadence, said that the first adopters of wide I/O will be "people who have space constraints and are not intimidated by 3D ICs. Right now that equates to the mobile sector."

Will wide I/O memory be a major driver for 3D IC design? Probably not initially, Neil said, because the people who adopt it are probably already investigating 3D ICs. But wide I/O memory will be "part of the ecosystem and infrastructure that will make it easier to decide to do 3D ICs," he said. 3D ICs can also be designed with LPDDR, but the justification for choosing a 3D IC with TSVs is not as compelling in that case.

The Cadence wide I/O offering includes a configurable memory controller, PHY (physical layer), and verification IP. It goes beyond the proposed JEDEC specification by including such features as traffic reordering, which helps provide an optimal data flow with the best possible balance of bandwidth and latency. Cadence also provides a comprehensive methodology and tool support for 3D IC/TSV design, including IC/package co-design, 3D-aware floorplanning and routing, extraction, thermal analysis, test, and custom/analog design as well as digital. That flow is described in a previous blog post.

Further information about wide I/O memory and its use in 3D ICs is available in a recent article in 3D Packaging magazine.

Richard Goering

 

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