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How Parasitic-Aware Design Flow Improves Custom/Analog Productivity

Comments(2)Filed under: Industry Insights, Virtuoso, Analog, DRC, PCells, modgens, LVS, PAD, parasitic-aware design, custom/analog, IC6.1.5, rapid analog prototyping, parasitics

Increasing complexity is making it harder and harder to converge on cost-effective custom/analog designs. But most attempts to radically reshape the custom IC design flow have not worked well. What's needed is a productivity aid that's conceptually easy to understand, works with existing tool flows and methodologies, and complements the "art" of handcrafted custom IC layout rather than trying to replace it with somebody's idea of automation.

Parasitic-aware design, part of a "unified" custom/analog flow that Cadence is announcing today (March 14, 2011) as part of the Virtuoso IC6.1.5 release, is such a productivity aid. The basic idea behind it is, quite simply, "the sooner the better." The sooner you can bring in information about parasitics and variability, the faster you can get to tapeout with a high-quality product, without the need to overdesign for unexpected parasitics. The idea is to bring parasitic information into front-end design long before a final layout is completed.

Today's Iterative Design Flows

In contemporary design flows, the circuit designer completes a schematic, runs some simulation, and hands the design over to a layout designer who does a beautiful, compact, hand-crafted layout. The layout designer runs design rule checking (DRC) and layout-versus-schematics (LVS). Then, when the layout is DRC and LVS clean, extraction is run to obtain the parasitic information from the layout.  Finally, the circuit designer gets parasitic information back - and this is when a loud "whoops" is often heard echoing through the halls.

"The way it's done today, you find problems too late in the design cycle," said Steve Lewis, product marketing director at Cadence. "Parasitics only show up with a fully extracted design. You might find suddenly that you can't meet the power spec because there's too much parasitic load sitting on your power rails."

The result is an iterative process that goes back and forth between the circuit designer and the layout designer. It's not an incremental flow, because designers have to wait for another LVS-clean layout to get parasitics. To avoid such iterations, one very common technique is to overdesign the circuit to compensate for unknown parasitics. That, of course, adds to area and cost.

Rapid Analog Prototyping

Parasitic-aware design offers an alternative through an approach called rapid analog prototyping. This allows the circuit designer to generate a quick layout and obtain some reasonably accurate information about electrical and physical effects, including interconnect and device parasitics, electromigration and IR drop, well proximity effects, and litho-induced variability.  A typical analog layout that would take two weeks to lay out by hand can be set up and run in about 4 hours.

The parasitic-aware design flow provides a quick estimation of post-layout parasitics.

Rapid analog prototyping is made possible with features in the Virtuoso 6.1.x releases, including SKILL PCells, Modgens (module generators), and automated routing. It can also leverage information from reused IP blocks. Rapid analog prototyping will build a DRC and LVS correct layout according to designer constraints such as matching, symmetry, and orientation.

Is the rapidly generated layout as compact and perfect as a handcrafted layout? No. Does it replace the custom layout designer? Again, no. "All it does," Lewis said, "is enable the circuit design engineer to have better information about critical areas during the design phase, and to provide better guidance to the implementation engineer when he's creating the final layout."

So how close is the prototype layout to the final layout? According to Lewis, in circuits with a lot of matching and symmetry, the two layouts could be 90% identical. With no matching or symmetry, they may be 50% identical. But that's still accurate enough to "give you a good sense of where your critical areas are," he said.

Parasitic-Aware Design and Silicon Realization

Parasitic-aware design is a good example of the EDA360 Silicon Realization concept, which focuses on unified intent, abstraction, and convergence. The parasitic-aware design flow maintains design intent through electrical and physical constraints, raises abstraction through pre-layout estimates, and speeds convergence on a manufacturable design.

To learn more about rapid analog prototyping and to see a brief demo, you can access an archived Silicon Realization webinar on this topic here. A feature story provides more information about the Virtuoso IC6.1.5 release, which provides many capabilities in addition to parasitic-aware design.

Richard Goering

 

Comments(2)

By George Storm on March 14, 2011
This is sensible as an intermediate-stage check - but it is still too late in the flow for maximum utility.  What is most needed at the first-simulation stage is parasitic-aware models, so that sensible well and substrate parasitics are included at the first stage.  At the present time this does not appear to come naturally to foundries; but the EDA companies could help by providing templates that allow designers to define diffusion and well arrangements from the schematic - and which would also generate the well parasitics without requiring the layout.  This should also in principle develop to extended LVS checks that the layout conforms closer to designer intentions.  
It will not be straightforward to do this well - we only need to look at the development of source-drain models and the resulting arbitrary numbering system of GEOMOD (and that still does not allow designers to define layout ordering even of the Source-Drains in a single DIFF region).

By adrian bratt on March 15, 2011
Interesting idea, but it remains to be seen how it rolls out in practice.
The trouble remains that interactions require full spice sims and that's not
easily done on designs at the top level, where there are a lot of devices and
some conflicting simulation requirements. Some blocks are GHz devices and
others take ms to settle, spectre just can't get it done in anything like a reasonable
time at full spice level.
Cheers
Adrian

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