Should the Universal Verification Methodology (UVM) work with SystemC? Should VHDL be extended with the object-oriented capabilities of SystemVerilog? Is it better to have interoperability between languages, or a unified language, or a language-neutral verification methodology? These questions and more were discussed and debated at a lively "town hall forum" lunch at the DVCon conference Feb. 28.
This unique event was sponsored by Accellera and the Open SystemC Initiative (OSCI), and moderated by Stan Krolikoski, group director of standards at Cadence and an officer in both organizations. Shishpal Rawat (left), Accellera chair, and Eric Lish (right), OSCI chair, were seated in front of the room. There was no set agenda and no slides. "This is a panel discussion, and you are all on the panel," Krolikoski told the audience.
What hadn't been expected is that around 300 people would attend. Some were at the conference for the co-located North American SystemC User Group (NASCUG), while others were attending a UVM tutorial. The event took place shortly after Accellera approved UVM 1.0, which includes support for the OSCI transaction-level modeling (TLM-2) interface.
Here are some verbal snapshots from the discussion that followed.
UVM and SystemC Should Get Together
Audience member: "UVM can be an addition or useful adjunct to SystemC. When you're modeling with SystemC, verification is a key component. People tend to model in an ad-hoc style. Perhaps we can have a more structured method. You need to get a good verification strategy in place to do high-level modeling."
Audience member: "We need to move that [UVM] technology to the SystemC environment so we can use it for architectural models. If it follows into virtual platforms, it gives me a clear base for developing synthesizable code."
Audience member: "I work at Infineon and we very much support a UVM implementation targeting SystemC...We need to define what methodology to use with SystemC, and how to bring it back to RTL. An open-source implementation of UVM for SystemC would really help out a lot."
However, Don't Go Too Far
Audience member: "We should not implement the sequence mechanism or low-level event-driven capabilities of UVM/SystemVerilog in SystemC. The strength of SystemC is its modeling capability. It's not event-driven like SystemVerilog is. We need to be very careful about not getting caught up in putting everything in one language."
Photo by Joe Hupcey III
Accellera and OSCI, Working Together
Rawat: "What's being discussed right now is how the two organizations can work more closely together. TLM-2 is a start."
Lish: "We're looking at how we can collaborate better. There's a recognition that gaps need to be closed...we need to make sure we don't duplicate efforts."
Value of a Reference Implementation
(Note: OSCI and Accellera have reference implementations for SystemC and UVM, respectively).
Audience member: "As an end user, having a reference implementation available is an enabler in the sense that it levels the playing field for us. It's a reference everybody can use. It's worth its weight in gold."
Lish: "A reference implementation helps further the standard, but OSCI is avoiding being a supplier of software technology. There's a fine line."
Audience member: "The term verification does need to be broadened. There's functional verification, performance verification, and also low power verification. All three angles need to be considered."
Where's the Language Interoperability?
Audience member: "Accellera is great at promoting different language standards, but there's no work on interoperability between languages. They did something about VMM and OVM but I don't see anything about SystemC and SystemVerilog."
Audience member: "Is interoperability and reuse between SystemC and SystemVerilog/UVM the way to go, or do you see a unification of languages?"
Rawat, in response to unification question: "Only when COBOL is retired."
Krolikoski: "Just speaking for myself, rather than having interoperable languages, I wonder if it's better to come up with a definition that's language agnostic and make sure the languages map to it."
Extend VHDL -- or Drop It?
Audience member: "Can we all agree it would be a complete waste of time to implement the object-oriented extensions in SystemVerilog in VHDL?" (Applause)
Krolikoski: "Should we have a SystemVHDL?"
Audience member: "Should we have VHDL?"
(At this point, Krolikoski asked how many people in the audience use VHDL, and around 25 out of 300 raised their hands. "This tells me there are a lot of VHDL users out there," he said).
Audience member: "I work for a defense contractor and we have to use VHDL. The government doesn't currently care about testbenches, so I use SystemVerilog for those, but as soon as they care about it, we have to hand in VHDL. Until EDA vendor tools become larger than the U.S. government, we have to do what the U.S. government wants."
Parting Comment: Avoiding "Standards for Pigeons"
EDA journalist Gabe Moretti, speaking from the audience, had the final word as he called for more participation in standards efforts. "Standards built in a vacuum are only good for pigeons," he said. "We need you guys to build useful standards." If you want to know what Gabe meant by "standards for pigeons," see his blog post on the Gabe on EDA site.