Mixed-signal verification is a tough challenge, and much of the difficulty lies with models. How can engineers choose the right modeling approach and guarantee that models accurately represent the silicon? A session at last week's (Feb. 17) Cadence "Tech on Tour" seminar provided some answers.
Cadence last week launched a series of "EDA360 Tech on Tour" Silicon Realization/Mixed-Signal R&D seminars. These full-day events will take place at several North American locations this week (listed below), and in Europe and Asia in March. Information and registration is available here. In addition to AMS behavioral modeling, topics include:
- Analog/mixed-signal simulation and verification
- Metric-driven verification for mixed-signal SoCs
- Power intent and verification in mixed signal
- Mixed-signal implementation challenges and solutions
- IR/EM analysis for mixed-signal designs
- Enabling interoperability through OpenAccess
The session I attended, AMS Behavioral Modeling, was presented by Walter Hartong, staff product engineer at the Cadence facility in Munich, Germany. It was packed with good information and presented to an attentive audience that mostly filled a large auditorium at the Cadence San Jose headquarters Feb. 17.
The Mixed-Signal Verification Dilemma
What mixed-signal designers really want, Walter said, is fast and accurate simulation of a full chip with the package. But SPICE can take weeks to finish, and digital simulation is fast but doesn't consider analog effects. You can run a small block on SPICE, but that doesn't tell you if the block works properly in the context of the chip.
There are several styles of behavioral modeling that can apply to mixed-signal designs. Walter identified three, all of which are supported by the Cadence Virtuoso AMS Designer:
- Conservative models with Verilog-A or Verilog-AMS. This approach uses an analog kernel, evaluates voltage and current, and solves Kirchhoff's equations. Models can be integrated into a full analog simulation. But, you could represent a band gap with hundreds of transistors with a few lines of code.
- Signal-flow models. Equations are easy to solve, but the signal flow is unidirectional. Models provide input/output feedback but no loading. This is useful for abstract analog models.
- Event-driven models. Here, code is evaluated only at events; simulation time grows linearly with the number of events. This is useful for digital, mixed-signal, and high-level models.
So when to use what? The conservative style provided by Verilog-A and Verilog-AMS is useful when there are significant accuracy requirements. This approach can potentially provide a 50-100X speedup over SPICE, but it all depends on how good your modeling is. "If you're a poor modeler, there's a chance you could end up with a model that's as slow as SPICE simulation or even slower," Walter warned.
Real number modeling, also available through Verilog-AMS with the wreal data type, brings real number values into event-driven digital simulation. It thus has the speed benefits of digital simulation and can leverage the metric-driven verification methodology that's increasingly used by digital engineers. It's good when there are hard performance requirements and limited accuracy requirements. For example, wreal is very useful for full-chip mixed-signal simulations.
The following chart shows the accuracy/speed tradeoff ranges provided by various analog/mixed-signal modeling alternatives. Note that the conservative modeling style has a broad possible range, depending on how good the modeling is.
Also important is the modeling effort. Here we can see that conservative models require the most amount of effort. "You can potentially spend days, weeks, months to develop good behavioral models," Walter said. Wreal models are relatively fast to develop because they're less detailed. An important rule of thumb: "Model what you need, not what you can."
How Do We Know the Models are Good?
Behavioral models are worthless if they don't accurately represent the silicon. Continuous model validation is necessary, Walter noted, because both designs and models change over time. One small change to a model or the design could invalidate the model.
Walter ran through a demo of amsDMV, a Cadence Virtuoso model validation tool mainly targeted at analog/mixed-signal. It provides an automated way to quickly run regression tests, but it's not a replacement for an analog designer who can do a detailed model validation. "Don't be scared it will replace your job," Walter said. "It doesn't know the details of the model or the circuitry, it just raises a flag if the simulation results are different from what they should be."
If this one session (out of 10 in the full-day seminar) is any indication, this is a very useful seminar series. It repeats in Boston Feb. 22, Austin Feb. 23, and Irvine, CA Feb. 24.
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