There's big news today (Feb. 18) in the functional verification world. As noted in various tweets from standards group members, the Accellera standards organization board has unanimously approved the Universal Verification Methodology (UVM) 1.0 as an industry standard for verification interoperability. Accellera is also offering a UVM tutorial at DVCon in San Jose, Calif. Monday, Feb. 28.
As has been noted in a number of Cadence Community blogs, as well as ongoing press coverage, UVM 1.0 will have a profound impact on functional verification. It establishes a standard, backed by all major EDA vendors, for verification IP (VIP) and testbench interoperability. Just having the SystemVerilog language as a standard is not enough. There's also a need for a standard methodology so that VIP and testbenches can be reusable and interoperable in different simulation environments.
In an earlier blog post Stan Krolikoski, group director for standards at Cadence, said that UVM is "the largest EDA standard/reference implementation effort since the original OSCI SystemC simulator was developed in the early 2000s." It's proceeded quickly, starting with a December 2009 vote to make the Open Verification Methodology (OVM) developed by Cadence and Mentor Graphics the basis of UVM. Cadence has been actively involved in this standards effort and literally "wrote the book" by publishing A Practical Guide to Adopting the Universal Verification Methodology (UVM) by Sharon Rosenberg and Kathleen Meade last year.
This morning, Stan said that "UVM represents a coming together of users and vendors of verification tools/environments to solve a major industry problem -- the existence and popularity of two incompatible verification methodologies, OVM and VMM. Rather than accept this state of confusion, the VIP Technical Subcommittee came together and produced a single verification methodology, UVM. With the approval of the UVM 1.0 standard and the subsequent release of the accompanying reference implantation and user's guide, the community will be able to develop verification IP that is interoperable across simulators and verification environments. This is a seminal example of industry leaders working as a team to harness the power of standardization for the good of both users and vendors."
What's New In UVM 1.0
The UVM 1.0 EA (Early Adopter) release was approved in May 2010. Since it was nearly identical to OVM 2.1.1., it was production ready -- but many design teams were hesitant to adopt it because of the "Early Adopter" label. UVM 1.0 adds a few features, including:
- A run-time phasing feature that will allow UVM verification components to control aspects of the simulation cycle such as reset, configuration, execution, and shutdown.
- A register package that will provide a connection between the description of registers and the verification environment to allow control, randomization, and coverage.
- Support for a subset of Open SystemC Initiative (OSCI) transaction-level modeling TLM 2.0 communication within SystemVerilog.
In short, the time to adopt UVM 1.0 is now. And the work isn't done yet. As noted in previous blog posts, Cadence would like to see the UVM standard extended to provide support for other design/verification languages such as e and SystemC. At DVCon, a Cadence paper will present UVM-MS, a methodology that brings metric-driven verification to mixed-signal design.
I expect that further information will be available at the Accellera and UVMWorld websites in the very near future. Meanwhile, welcome to a new world of interoperable functional verification methodologies.
Stan Krolikoski reflects on the passage of UVM 1.0 today in his Chip Design Magazine blog post.
Recent Cadence Community blogs about UVM 1.0:
Adam Sherer: "We Want UVM 1.0! When Do We Want It? Now!"
Tom Anderson: A Quick Check on the Status of UVM 1.0
Richard Goering: Q&A: An Update on the Accellera UVM 1.0 Verification Standard