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Panelists: FPGA Tool Opportunity is at the System Level

Comments(2)Filed under: Industry Insights, FPGA, ESL, Qualcomm, Xilinx, DesignCon, EDA360, system-level, system level, Taray, Hogan, Altera, FPGAs, Gaterocket, FPGA tools

FPGA designers in the past got by with free or low-cost tools, and didn't provide much revenue for EDA companies. According to panelists at DesignCon Feb. 1, those days are going fast. A new era of complex FPGAs is opening a tremendous opportunity for new EDA support, especially at the system level, panelists said.

One scenario that emerged from the discussion is this: thousands of application developers writing software for FPGA-based subsystems, and accelerating portions of those applications with software. These developers need tools that let them work well above the register-transfer level (RTL). While FPGA vendors will support the flow from RTL on down, everything at or above RTL is fertile ground for EDA innovation.

The panel was moderated by veteran EDA investor Jim Hogan. Panelists included:

  • Botao Lee, senior staff engineer, Qualcomm
  • Dave Orecchio, president and CEO, GateRocket
  • Jay Schleicher, director of software engineering, Altera
  • Nagesh Gupta, engineering group director, Cadence (and founder of Taray before its 2010 acquisition by Cadence)
  • Vin Ratford, senior vice president, Xilinx

Coincidentally, the panel occurred one day after Xilinx announced its acquisition of AutoESL, a high-level synthesis startup.

140,000 Applications Developers

As FPGA devices approach 2 million logic cells, Ratford noted, existing tools are running out of steam. He advocated what he called "peaceful co-existence" between EDA and FPGA vendors. In his view, FPGA vendors will continue to focus on RTL-to-bitstream, with special attention to speeding up compilation times for large FPGAs. EDA vendors will provide "front end" technologies like high-level synthesis, system-level IP integration, verification, and virtual platforms.

If FPGA vendors build the right libraries, and EDA vendors build the right tools, "I think we can turn thousands of designers loose," he said. These developers will use pre-configured FPGA-based subsystems as applications platforms. "They're going to start in C, write their applications, then figure out what they're going to put into the FPGA fabric. I'd like to see 140,000 people building applications on FPGAs -- and not have to do that in RTL." Given that Xilinx signed up 35,000 new users last quarter, that's not a stretch.

"The area that I think is most interesting, in terms of EDA innovation, is really at the high level," Schleicher said. "There's a new class of designer that's a hybrid between an FPGA/ASIC and software developer. There's a real opportunity to make a business there." Meanwhile, he noted, Altera is looking at ways to "take the natural parallelism that exists in FPGAs and expose it in ways that make sense." One possibility involves leveraging the Open Computing Language (OpenCL).

"What I've heard so far is that the [FPGA] fabric itself is vendor proprietary," Hogan said. "The real opportunity is in SoC Realization, in Cadence speak." (This is a reference to the EDA360 vision paper, which describes application-driven design in very similar terms to what was discussed at this DesignCon panel).

Verification and Pinouts

Two other topics emerged at the panel - verification, and optimizing FPGA pin assignments on printed circuit boards. Ratford noted that many FPGA designers are turning to big EDA companies for verification support.  (Indeed, an Industry Insights blog post last week featured an interview with a Teradyne engineer who uses Cadence metric-driven verification tools for FPGAs).

Orecchio noted that "there is a tremendous opportunity in the verification space for people doing high-end FPGAs." What's needed, he said, is a way to bring the power of FPGAs "forward" into the simulation environment. His company, GateRocket, provides a hardware-assisted debugging tool for FPGAs.

Taray developed technology that optimizes pin assignments during PCB/FPGA co-design. This is critical because, as Gupta noted, FPGA pins can be configured any way the designer wants. "If you just look at FPGA timing," he said, "you can create pinouts that increase the number of board layers and do not reduce signal integrity."

Qualcomm's Lee brought forth a user point of view. He identified four challenges that call for better tool support:

  • The implementation process takes too long for big FPGAs
  • The tool chain is hard to debug
  • Simulation can be slow, or inaccurate
  • It's hard to verify and optimize pin assignments for FPGAs

FPGA designers will pay for tools, he said, if they help get the design done faster.  While FPGA device capability has evolved faster than tool support, "I'm very optimistic," he said.

Richard Goering



By Dave Orecchio on February 3, 2011
Thank you for the thorough coverage Richard.  
As FPGAs take on more applications and increase in complexity, software is important but these devices also need to be verified at the implementation level in market-realistic time frames something I like to call Device Native verification.  Using the FPGA as a turbo charger to the simulator enables the verification team to keep pace with the project time line while the device complexity escalates with each new FPGA technology node.  
Part of the EDA360 mantra, silicon realization is a broad concept that addresses the requirements and solutions to create a deterministic path to a successful silicon device.  Unlike IC design, the FPGA design process lacks the traceability through to silicon.  By integrating the FPGA into Incisive, like GateRocket does, the loop is closed between silicon and design and a significant gap to silicon realization for FPGAs is addressed.  That is why Hardware-Assisted verification for FPGAs is critical to the successful growth of the FPGA market.  
Dave Orecchio
CEO, GateRocket, Inc.

By Moshe Genish on February 6, 2011
Hi Dave,
I agree with you, this is a big step, how ever it require collaboration of FPGA Vendors and EDA tools to address this issue,
In addition FPGA vendor will have to speed up the compilation times for large FPGAs.
Moshe Genish
HW Leader PMC-Sierra

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