As the EDA360 vision paper notes, tool and methodology support is needed for IP integration into systems-on-chip (SoCs). A standards-based ecosystem needs to be part of this approach. One standard that can play an important role is IP-XACT, which provides a metadata documentation format for packaging, integrating, and reusing silicon IP blocks from different sources.
A newly archived Cadence System Realization Alliance webinar explores the role of IP-XACT in transaction-level modeling (TLM). The webinar was presented by System Realization Alliance partner Magillem, a French company that offers products and services for IP-XACT deployment. Their products include Magillem Platform Assembly, a tool that guides the SoC designer through virtual platform assembly and IP configuration. As noted on the Magillem web site, this product is tightly integrated with the Cadence Incisive Enterprise Simulator.
IP-XACT was developed by the SPIRIT Consortium, which merged into the Accellera standards organization last year. Officially, IP-XACT is now the IEEE 1685 standard. It provides a human-readable format for interoperable IP module descriptions and tool interfaces. Deliverables include an IP metadata schema, bus definitions, component schema, syntax and schematic rules, configuration and generation interfaces, and standard interfaces to tools.
SystemC and IP-XACT "Convergence"
In the webinar, Suresh Jeyachandran of Magillem discussed the use of SystemC and IP-XACT in virtual platform environments. "We know that the convergence between SystemC and IP-XACT is natural, and will contribute to a strong and coherent solution," he said. He went on to note that current models and platforms rely mostly on proprietary languages and formats, including pure C++ and specialty flavors of SystemC. With multiple IP providers and multi-site design teams, this lack of standardization is becoming a bottleneck.
SystemC makes it possible to design models based on common definitions and coding rules, and comes with protocol libraries, compilers, and simulators. IP-XACT provides an "electronic data book" that supports connectivity, abstraction definitions, configuration, memory management, and assembly information. It allows the generation of a variety of files for verification, test generation, documentation, packaging, and software.
The Magillem Platform Assembly tool includes an IP editor, register editor, API support, version management, and IP-XACT generation from legacy models. It can also generate header files, register files, and a "TLM skeleton." Incisive provides TLM-aware verification and debugging along with testbench automation and support for the Universal Verification Methodology (UVM). Cadence also provides high-level synthesis with C-to-Silicon Compiler. The result, said Jeyachandran, is a "complete TLM flow."
Users evaluate IP-XACT
Separately, an informal user survey on IP-XACT was posted last year by David Murray of Duolog. It's an interesting look at how the standard is used, and what parts of it are most successful. It also looks at requested future enhancements. One such request is to become more of a system-level standard and address software. That's a challenge that a number of our "EDA" standards have - how to adapt to a changing design environment in which software is increasingly the main cost and the largest bottleneck.
The archived Magillem IP-XACT webinar is available here. It requires Cadence Community membership (quick and easy registration if you don't have it already).