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New Silicon Realization Design Methodology Boosts 3D ICs With TSVs

Comments(0)Filed under: Industry Insights, TSVs, Encounter, SiP, Co-Design, 3D, Silicon Realization, codesign, analysis, test, 3DIC, 3D IC, 3D-IC, thermal, extraction, QRC, iJTAG, routing

Cadence this week (Jan. 31) is announcing a "unified" 3D IC design methodology that drives creation, implementation, and verification across the digital, analog, and packaging domains. It's part of a larger announcement of a digital end-to-end flow. What follows are some more details on how the new 3D IC methodology works.

First, a reminder on some of the challenges. As was noted in a recent Cadence whitepaper, 3D ICs with through-silicon vias (TSVs) do not require a revolutionary new design system, but they do require improvements to existing tools for floorplanning, routing, extraction, timing and signal integrity analysis, thermal analysis, and test. A point tool approach won't work. A unified solution that encompasses digital implementation, analog/mixed-signal design, and IC/package co-design is needed.

What's most needed is a Silicon Realization approach. Part of the EDA360 vision, Silicon Realization calls for three qualities: a unified expression of design intent, appropriate use of extraction, and convergence with electrical, physical and manufacturing data. A Silicon Realization solution for 3D ICs would provide a way to define the stacked die configuration (design intent), represent features on adjacent top and bottom die (abstraction), and converge on a manufacturable solution with analysis and packaging tools.

3D IC with silicon interposer layer, TSVs and 6 die

What follows is a brief overview of the Silicon Realization 3D IC methodology cited in the Jan. 31 announcement.

IC/Package Co-Design

Wait a minute - doesn't package design come last? No, that's the old throw-it-over-the-wall methodology, and that won't work for stacked die. Early in the design process you can use the Cadence SiP Digital Architect and its System Connectivity Manager utility to build a top-level netlist, make optimized I/O connections, create a package layout, and create die abstracts that are imported into the Encounter Digital Implementation System. Without co-design, the package may end up being more expensive than the silicon.

3D IC Implementation in Encounter

To represent the design intent of the die stack, you need three files: the top-level netlist mentioned above, an XML file that defines the stack configuration, and a power connectivity file. A graphical stacked die editor can create the XML file. Once the design intent is brought in, you can create TSVs and front and back-side micro-bumps, optimize their locations, and assign signals and power and ground to the bump arrays. You floorplan and route one die at a time, but abstracted views of adjacent (top and bottom) die tell you what's on those surfaces.

You then route signals, and power and ground, to the bump arrays. The Encounter Digital Implementation System's flip-chip router, as well as NanoRoute, have been enhanced for TSV routing with front and back-side bumps. Finally, you can run a connectivity check to make sure micro-bumps on adjacent die are properly aligned.

Extraction and Analysis

The next step is extraction and analysis. The Cadence QRC Extraction tool has been enhanced to extract TSVs and back-side metal redistribution layers (RDLs) in a single netlist. Encounter timing, IR drop, and thermal analysis tools have been enhanced to handle complete 3D die stacks. (Thermal signoff is important for 3D ICs, especially for die in the middle of the stack). Finally, the Cadence Physical Verification System has a 3D IC and TSV checker.

The Cadence Encounter Test product line has many design-for-test (DFT) and automatic test pattern generation (ATPG) features that are useful for 3D ICs, and Cadence is deeply involved in efforts to standardize IEEE 1687 internal JTAG (iJTAG), which can embed test structures in stacked die. Finally, the Cadence Virtuoso environment has added the ability to edit, draw, and save a 3D design; support TSV and RDL back-side routing; edit supported 3D objects; and trace connectivity through TSV and RDL back-side routing.

3D IC Design to the Mainstream

Cadence has used this flow with early adopters and has been engaged in successful tapeouts. The industry's real challenge, however, is one of bringing 3D ICs into mainstream design flows and volume production. As I said in a previous blog, the costs of design and manufacturing must be sufficiently low to allow this adoption.

Quoting from another previous blog, no semiconductor company will adopt 3D ICs because the technology is "cool" (even though it is). They'll adopt the technology to make money. Design tools and flows must make that possible. The Silicon Realization 3D IC design methodology announced Jan. 31 is a significant step in that direction.

This 3D IC methodology was part of a larger digital end-to-end announcement aimed at paving the way for the next generation of giga-gate, giga-Hertz designs. A feature article here has more information.

Richard Goering



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