A new standards effort that could ease low-power silicon IP integration is quietly underway at the Silicon Integration Initiative (Si2) Low Power Coalition (LPC). Although the LPC is probably best known as the home of the Common Power Format (CPF) originated by Cadence, it actually has a much broader role, and its power modeling efforts are not connected with any format or database.
The LPC, according to its web site description, is "responsible for the development of standards and enabling materials to support low power design by taking a flow-centric view from ESL to GDSII." Members include Apache, ARM, Atrenta, Cadence, Calypto, Entasys, IBM, LSI, Magma, and Renesas. At present its two most active working groups are the Model and Format groups. (The Format group recently completed CPF 2.0, scheduled for public release in February 2011).
The Model group is chaired by Dave Hathaway, senior technical staff member at IBM's Design Automation Labs. "We're trying to improve the state of power modeling of IP within design flows, and we've identified certain things we think are deficiencies or areas where that modeling could see some improvement," he said. Rather than develop a brand-new standard, he noted, the working group is working with the Liberty Technical Advisory Board (TAB) to improve power modeling within the Liberty (.lib) format.
The intent of the power modeling effort, said Ken Potts, LPC chair and director of strategic alliances at Cadence, is to "provide a standard so everybody can be on the same page when it comes to describing things that are impacting power design decisions across the SoC. That's a huge productivity challenge. If we can remove some of the energy that's going into everybody's one-off power modeling spreadsheets, that should result in efficiency for the design community."
Why Liberty Isn't Enough
Doesn't Liberty already provide some support for power modeling? It does, Hathaway noted, but Liberty is really aimed at small IP blocks such as standard cells. Large IP blocks have far more potential states and are more difficult to model. Thus, the Model working group has come up with two proposals that aim to provide more efficient, and more compact, power modeling for large IP blocks.
One proposal has to do with non-mutex (non mutually exclusive) modeling. The problem is that Liberty requires all power states to be mutually exclusive, leading to a state explosion for IP with many internal states. The proposed solution is a new construct that allows non-mutually exclusive power state modeling. The second proposal concerns "atomic" modeling. Today it is difficult to accurately model IP power in Liberty without modeling all internal transitions. The proposed solution would make it possible to model the power consumption of complex IP blocks without use of lower-level data.
These proposals are described in a 2010 requirements document available for download to anyone with a free OpenEDA account.
Variability and ESL
In 2011, the Model working group expects to finish some work on power variability and submit it to the Liberty TAB. The idea here is to define "power contributor models" rather than putting the power and energy values for each cell state and transition directly into a Liberty model. Each power contributor model type would capture a given cause of power dissipation, such as capacitive switching, short circuit or cross-over current, and leakage.
This approach is needed because power dependencies, especially for leakage, are very complex, Hathaway noted. Power contributor modeling allows these complexities, including dependencies on voltage, temperature, and different aspects of process variability, to be modeled once for the technology rather than folded into every cell leakage state.
Further down the road, the group intends to work on electronic system level (ESL) power modeling. Such models would identify power consumption at a high level rather than describe it in terms of individual signal transitions. This work would follow naturally from earlier work in the LPC that defined an RTL-to-implementation low-power reference flow.
The power modeling initiative is heavily backed by IBM and supported by EDA vendors including Cadence. The benefit? "A lot of what we're doing for large IP blocks are things people already do in their own custom way," Hathaway said. "By incorporating what people are already doing in spreadsheets, the standard will facilitate IP exchange and make it easier for vendors to supply tools."
A Broader Vision
The EDA360 vision paper published by Cadence emphasizes the need for better tool support for IP integration, backed by a standards-based ecosystem. Given the prevalence of low-power design, a power modeling standard that works for large IP blocks could be an important part of that ecosystem.