Much happened in the world of EDA and electronic design in 2010, and this year-end blog post provides a quick summary of ten developments I thought were particularly notable. Some received considerable publicity, while others were hardly noticed. The list below does not include any product announcements, but does include standards developments, technologies, reference flows, and a notable vision paper.
To avoid any implied ranking, this list is alphabetical. After each item, I've listed one or more Cadence Community blogs with more information. If you think I've left something out, let me know. Best wishes for the oncoming New Year!
Analog/mixed-signal at 28nm - who says analog doesn't scale? In 2010, GLOBALFOUNDRIES and Cadence worked together to develop a 28nm analog/mixed-signal development kit. Similarly, TSMC's Reference Flow 11 provides an analog-mixed-signal reference flow for 28nm.
Analog/Mixed-Signal at 28nm - An Inside Look
ARM Cortex-A15 - this is a remarkable new multi-core processor that claims a 5X performance gain over today's best smartphone processors, with a comparable energy footprint. The interesting side story is how ARM, Cadence, and Texas Instruments worked together early in the processor's development cycle to get a head start on EDA tool support. This experience takes multi-vendor collaboration to a new level.
ARM Cortex-A15: Unusual Early Collaboration Gives Designers a Head Start
DRC Plus - can design for manufacturability actually get easier as process nodes shrink? That possibility is offered by DRC+, a new pattern-based technology developed by GLOBALFOUNDRIES in collaboration with Cadence and Mentor Graphics. It uses shape-based pattern matching to identify lithography hot spots.
How DRC Plus Makes DFM Easy at 28nm
EDA360 - presented as a vision for the entire industry, the EDA360 vision paper published in April describes a broadened mandate for electronic design automation. It's based on the realization that software applications are now the primary differentiator for systems companies and their end customers, and it charts a new course for both hardware and software design. Dozens of Cadence Community blog posts this year have discussed EDA360; the following three will provide a basic introduction. For some deep and colorful insights, see Steve Leibson's EDA360 Insider blog.
John Bruggeman Q and A: Explaining the EDA360 Vision
Ten Key Ideas Behind EDA360
CDNLive! - Cadence Outlines Strategies for EDA360 System, SoC, and Silicon Realization
ESL Methodologies - Lots of electronic system level (ESL) tools exist, but this year brought a strong focus on coherent methodologies and flows. Virtual prototypes, high-level synthesis, emulation/FPGA prototyping, and transaction-level modeling (TLM) based verification all need to work together. A new book, TLM-Driven Design and Verification Methodology, shows how this can be done.
TLM-Driven Design And Verification Methodology Book Author Interviews
Author Roundtable: New TLM Design and Verification Book
Linaro - this open-source effort seeks to ease Linux development on ARM-based SoCs. Linaro has profound implications for the entire SoC development chain, including hardware design, embedded software design, and systems and application development.
Why SoC Designers Should Care About Linaro
OpenPDK - this Silicon Integration Initiative (Si2) standards effort, launched in May with support from ten founding members including Cadence, Mentor Graphics, and Synopsys, seeks to define a "single source" of foundry process data from which vendors can compile unique PDKs. OpenPDK could lower costs and speed the deployment of new processes.
What OpenPDK Is and Why It's Important
Webinar: Cadence, Mentor Find Common Ground on PDK Standards
3D ICs with TSVs - while there was no one "big" development in this area, 3D ICs are moving closer to production flows. Design and manufacturing requirements are becoming better understood, tools are adapting, and a supply chain ecosystem is forming. The list below includes the most recent of a number of 2010 Cadence Community blogs on 3D ICs.
Whitepaper: 3D ICs Pose Design Challenges, But No "Showstoppers"
3D-IC TSV Realization: The Race Has Begun!
3D-IC TSV Update: No Technology Roadblocks, But Cost Management is Needed
TSMC Reference Flow 11 - this reference flow is especially notable because it includes ESL, thus representing a strong endorsement of system-level design by the world's largest foundry. It covers virtual platform modeling; power, performance, and area-aware models; ESL verification; and high-level synthesis. Reference flow 11 also adds support for 3D ICs with through-silicon vias (TSVs), and as noted above, provides an analog/mixed-signal reference flow for 28nm.
What Cadence and TSMC Learned from ESL Reference Flow 11
Cadence Contributes ESL Methodology to TSMC Reference Flow 11
Universal Verification Methodology (UVM) - at the end of 2009, the Accellera Verification IP subcommittee voted to make the Open Verification Methodology (OVM) the basis of the new UVM standard. An "early adopter" (but production ready) UVM 1.0 release came out in May, with the full UVM 1.0 release expected in early 2011. This is an essential standard for verification IP interoperability. There have been many Cadence Community blogs about UVM; three recent ones are listed below.
Q&A: An Update on the Accellera UVM 1.0 Verification Standard
"We Want UVM 1.0! When Do We Want It? Now!"
A Quick Check on the Status of UVM 1.0
Thanks for reading, and Happy New Year to all!