Integrating silicon IP into systems-on-chip is a lot harder than it used to be - but there are some emerging trends that will help, according to panelists at the EE Times System-on-Chip 2.0 virtual conference Nov. 18. Three topics stood out for me - the emergence of IP subsystems, the avoidance of multiple legal entanglements, and the integration of IP from multiple vendors.
The panel was moderated by Dylan McGrath, online editor of EE Times. Panelists included the following (sorry, no photo - this was an on-line conference).
- Rick Tomihiro, director of marketing, semiconductor IP, Xilinx
- Frank Ferro, director of product marketing, Sonics
- Steve Leibson, EDA360 evangelist, Cadence
- Kalar Rajendiran, senior director of marketing, eSilicon
The panel was conducted in a Q&A format. Below, I've selected three questions that reflect the topics mentioned above, plus some answers. Separately, Steve Leibson wrote out his answers to all of the questions asked at the panel in an EDA360 Insider blog post.
Question: There's a lot of talk about IP subsystems. What's behind this trend, and how does it affect the IP market and selection process?
"We're seeing, on average, 50 IP blocks on SoCs," Ferro said. "If you really look at it there are SoCs with 100 or 200 IP blocks. To individually purchase that many [IP blocks] is just getting difficult. What we're seeing now is a lot of IP grouped together in functionality, like a video subsystem with all its pieces."
The industry today has a very limited idea of what IP is, Leibson said. "We think it's just RTL but it's really more than that. It's also the verification IP that goes along with the design IP, so you can verify that the IP will do what you think it does. It's also the software drivers that make this thing go from a system perspective. And it's the protocol stack, because very few people want to become experts on what this block is doing."
Rajendiran noted that there are two classes of subsystems - peripheral subsystems and functional subsystems. Peripheral subsystems are available already, but functional subsystems are going to take a collaborative effort. "I don't think an IP company can just say, here's a subsystem, I'll sell the same thing to 10 different companies," he said. "In my opinion it's not going to be off the shelf."
Xilinx, Tomihiro noted, offers pre-integrated, pre-verified reference designs that customers can use or modify. Next year, he said, Xilinx will offer "pre-integrated hardened subsystems" including Cortex-A9 processors, PCI Express, USB, Gigabit Ethernet, DDR, NAND flash, and peripherals. These subsystems will be integrated with the FPGA fabric.
Question: What's holding back the use of more third party IP?
Leibson identified two problems. One is that customers don't know how to assure they're getting quality IP, and the other is legal entanglements. "As long as every piece of IP you acquire requires a long contractual negotiation between two teams of lawyers, engineers will run from that as fast as they can," he said. "We need something along the lines of the Apple iTunes store, where you can click on a piece of IP and use it. When we get there, that's what will crash the barriers against using IP."
Ferro noted that Sonics is using a cloud computing model with one if its IP offerings, which side-steps the need for customers to sign legal contracts to evaluate it. (I am presuming this is a reference to SNAP, or Sonics Network for AMBA Protocol, which Cadence is also reselling. I wrote a recent blog that mentioned this product and its availability through a cloud computing model).
As a value chain producer, Rajendiran noted, eSilicon "has made it easier. Anybody doing a chip with us doesn't have to sign 10 or 20 different documents. We have agreements with most of the major IP providers." The bigger concern, he said, is whether the IP is going to work in the customer's "operating condition."
Question: What efforts have been made that will allow IP blocks from multiple vendors to work together?
"Whether OCP or AMBA or IP-XACT or IP encryption, standards are the key to getting independent IP blocks from different vendors to play together nicely," Tomihiro said. He noted that Xilinx is releasing an IP-XACT package in the next quarter.
Ferro noted that Sonics offers interconnect IP that allows everyone's IP, even non-standard blocks, to work together. Even so, the company is a strong advocate of Open Core Protocol (OCP) and AMBA. Ferro cautioned that "even within AMBA everyone doesn't implement exactly the same." He said "it will be a while before there is true plug and play among vendors."
"Standards are number one," Leibson said. "Number two is finding some sort of body, whether commercial or an association, that is going to confer certification of compatibility. That is yet to come."
Rajendiran struck a note of caution. When one moves to the physical domain, he noted, it is still difficult to get IP from multiple vendors to work together nicely. There are many potential problems, such as incompatible I/O signaling levels. "There needs to be collaboration and uniformity in terms of how to make it work in the physical domain."
Rajendiran got in the last word at the panel: "Complexities have increased from the system level to the implementation level. We all have to work together."