Home > Community > Blogs > Industry Insights > arm techcon ibm speaker outlines path to 22nm and beyond
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more convenient.

Register | Membership benefits
Get email delivery of the Industry Insights blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

ARM Techcon: IBM Speaker Outlines Path to 22nm and Beyond

Comments(0)Filed under: ARM, lithography, IBM, SOI, EUV, Double Patterning, nanotechnology, source mask optimization, SMO, 20nm, 22nm, Patton, ARM Techon

An IBM industry address at this week's ARM Technology Conference (ARM Techcon) included both inspiration and a warning. The inspiration came from optimistic descriptions of the technologies that will propel us to 22nm and below. The warning was that it takes at least 10 years to bring new silicon technologies from research to deployment, making long-range R&D and collaboration more important than ever.

The address was titled "Semiconductor Technology Innovation at 20nm and Beyond," and was given by Dr. Gary Patton, vice president of IBM's Semiconductor Research and Development Center. It stressed two key themes -- innovation and collaboration.

Early in his talk, Patton reviewed the technology innovations that have brought us to today's advanced nodes. These include copper interconnects, silicon-on-insulator (SOI) substrates, strained silicon, multi-core processors, immersion lithography, and high-k metal gates (HKMG). Upcoming innovations include 3D stacked die and carbon nanotubes.

Well and good, but the cost of doing all this development has gone up "exponentially," there are only a few independent R&D centers remaining, and all of these technology innovations took over 10 years to develop, he noted. The only way forward is collaboration on many levels. For IBM, this includes collaboration with equipment and material suppliers, EDA vendors, and of course ARM, which worked with IBM to co-develop 32nm, 28nm, and 22nm process nodes. Today, Patton noted, the 22/20nm work is "fully engaged."

Double Patterning and Source Mask Optimization

Patton noted four key areas that are important to the 22nm discussion: lithography, device architectures, carbon electronics, and 3D. He spent the greatest amount of time talking about lithography. "We have a real discontinuity at 22nm," he said. "There is no new [lithography] tool that provides a better wavelength or numerical aperture." We've had a "great run" for the last 25 years by improving both, but that's over now, he said.

There are only two possible techniques for 22/20nm lithography, he said; double-edge/double expose (double patterning), or source mask optimization (SMO). He described SMO as an alternative to the high cost of double patterning. With SMO, he said, "we relax restrictions on the light source so it is not a fixed light source. It is a pixilated and programmable light source. Then, by using computational techniques, we can co-optimize the light pattern we want to produce with the mask."

I previously wrote a blog about double patterning in which I said the technology "will probably be required at 22nm and below." If SMO turns out to be a practical, cost-effective alternative, perhaps double patterning won't be required.

Of course, this entire discussion will become a moot point when extreme ultraviolet (EUV) lithography comes on line. Patton said that double patterning will be essential at 14nm unless EUV is available, and concluded that we "really need EUV" below 15nm. IBM is working on this technology. But it's very different from current lithography. It needs a high vacuum, uses a different wavelength, and requires new masks and new resists. "A lot of collaboration and a lot of work is needed to make EUV ready for 15nm," he said.

New Devices, Nanotechnology, and 3D

Patton also talked about some innovations that will be needed to support scaling beyond 22nm:

  • New device structures such as FINFETS or extremely thin, fully depleted SOI
  • New interconnect materials and structures to reduce coupling and improve resistivity
  • Carbon nanotechnology, which will allow "extraordinarily high carrier mobility"
  • 3D stacked die, which will improve bandwidth and place a lot of functionality in a small space

Research is ongoing in all these areas. But again, there's a warning - "these innovations take ten years or more to get from the research stage into the hopper."

Patton's opening remarks actually provided a nice summary of his talk. "There's never been a more exciting time to be in technology development," he said. "It's all about innovation. It's also all about collaboration with a wide range of suppliers in the marketplace."

Richard Goering

Photo by Joe Hupcey III

 

Comments(0)

Leave a Comment


Name
E-mail (will not be published)
Comment
 I have read and agree to the Terms of use and Community Guidelines.
Community Guidelines
The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.