As described in the EDA360 vision paper, the integration of both hardware and software IP is overtaking design creation as the primary challenge for many design teams. What are the implications of this seminal shift? Some interesting perspectives emerged from a panel at the recent CDNLive! Silicon Valley, at which panelists from ARM, GLOBALFOUNDRIES, Open-Silicon, and IBM discussed trends ranging from hardware/software integration to the 14nm process node.
The panel was moderated by Vishal Kapoor, vice president of product management and strategic business alliances at Cadence. Panelists (left to right in photo below) included:
- John Goodenough, worldwide director of design technology, ARM
- Walter Ng, vice president, IP Ecosystem, GLOBALFOUNDRIES
- Naveed Sherwani, president and CEO, Open-Silicon
- Sue Bentlage, EDA functional development manager, IBM
Panelists discuss SoC integration issues at CDNLive! Silicon Valley
Here are some interesting points that stood out for me.
The need for "excellent" interoperable IP
"Our mission is to deliver differentiation, and to do that effectively we need to make sure that IP is going to be realized in SoCs and in downstream products," John Goodenough said. "The only way we can address that is to attack integration costs, and by partnering early with all our ecosystem partners to ensure our IP interoperates with the tool flows. And more than that, it needs to be excellent in that interoperability to achieve power, performance and functionality goals."
Concurrent process and IP development
Foundries are having to do concurrent process and IP development, according to Walter Ng. "Customers expect that as we release a new design process, we have IP already proven in silicon."
The "Design Lite" trend
Naveed Sherwani noted that many of his customers want to do derivative designs, with extensive IP reuse. "I think this is a new trend we call Design Lite," he said. "The whole idea is that the EDA companies, design teams, and IP providers work together to turn around a chip not for $50 million, or $90 million, or $120 million, but for $10 million or $5 million."
Does "SoC" mean "software on chip?"
"I think software is the key to differentiation," Goodenough said. "When you're looking at SoCs, it is software on chip." Sherwani noted that with derivative designs, it is often sufficient to just change the software without touching the hardware. Sue Bentlage said that "from an IDM perspective, our focus right now is on Silicon Realization with the integration of more complex IP with the software."
How end consumers are changing the foundry business
Ten years ago, Ng said, he wouldn't have expected that silicon would be driven by end consumer applications. But that's the case now, and "in reality it's causing a ripple effect back through the supply chain, and we are having to do things differently, and serve different types of customers than traditional foundry customers." With the new batch of customers, cost and time-to-market are key.
Challenges at the hardware/software boundary
One challenge, Goodenough said, is getting early estimates of performance and power to ensure the system architecture is correct. Another is validating that the OS and applications run correctly. To achieve this step, "there's an awful lot of emulation and prototyping that's used early."
"Real software engineers are a completely different breed of people, and the challenge lies in talking to those guys who are thinking about what will be in the operating system next," he said. "A lot of modeling work relies on ensuring that we can move some of the hardware capabilities upstream, so the OS can take advantage of them."
What will 14nm look like? Will there be a magic button we can push?
"I wish there was," Ng said. At 14nm, he said, "Silicon Realization is possible only if collaboration becomes a lot more tight." Functionality alone is not enough. "It's great to be able to design, but to make sure you can design it and print it and yield it in the package is the biggest challenge. That is going to require a lot more coordination in the ecosystem."
Goodenough pointed out that designs at older process nodes will still be widely deployed. "Productivity and integration are applicable not only on the leading edge, but also rely on making integration as quick and turnkey as possible on the older nodes."
Moderator Vishal Kapoor summed things up as follows: "It's really interesting that what we've talked about here - everything from software down to 14nm - requires collaboration. We've got to bring everything together."
Photo by Joe Hupcey III