EDA360 was announced in April as a vision for the entire EDA industry. This vision of application-driven design has attracted a good deal of attention since then. What hasn't been much discussed -- yet -- is the Cadence strategy for realizing the vision. In a packed auditorium, attendees at CDNLive! Silicon Valley Oct. 26 heard several talks that presented key elements of that strategy.
The strategy addresses the three capabilities described in the EDA360 vision paper. Here's a quick review:
- System Realization is the creation of a hardware/software platform ready for applications deployment, including the software stack up to the applications level.
- SoC Realization is the completion of an individual system-on-chip, including "bare metal software" such as drivers.
- Silicon Realization represents everything it takes to get a design into silicon. In contrast to point-tool based flows, it provides a deterministic, end-to-end path to predictable silicon.
As I noted in yesterdays' blog posting, Silicon Realization was a prominent theme at CDNLive!, and a new whitepaper provides a detailed explanation of how it differs from EDA as it's known today.
John Bruggeman, Cadence chief marketing officer, started the strategy discussion with a look at System Realization. He first noted the importance of models and the difficulty of finding or developing the right models. "A proprietary approach will not work," he said. "The first element of our System Realization strategy is around an open standards-based ecosystem that is creating and delivering the models you most need to represent your system."
Once you have the models, you need a "virtualization platform," Bruggeman said. But this differs from the "virtual platforms" available today. What's really needed, he said, is a single platform that serves different users, including software developers who need extremely fast models and hardware developers who need cycle-accurate models. This can only be done with a common data model.
John Bruggeman discusses EDA360 strategy at CDNLive!
Finally, Bruggeman said, "we will provide tools to help you plan and architect your system, so you can reuse the models, integrate and analyze them. You can discover what the performance is, what the leakage is, and whether you've met the intent of your system design."
And there's one more key element in the strategy -- a deterministic path to SoC Realization.
SoC Realization, Bruggeman said, is "where we deal with bare metal software, and it starts with IP." He noted that some large customers are spending $3 to $5 on integration and verification for every $1 they spend to purchase IP. "That doesn't make sense," he said. "Why wouldn't a company like Cadence provide optimized, integrated IP stacks and strip these inefficiencies out of the supply chain?" This summer, in fact, Cadence introduced an integration-optimized USB 3.0 IP stack.
Beyond IP stacks, Bruggeman said, "we will deliver tooling with a design environment to enable you to attack integration. Rather than focusing on delivering component IP, he said, Cadence will help users do more with component IP, plan and architect SoCs, integrate and verify IP, and create IP. Most importantly, this integration environment "will connect down to Silicon Realization in a deterministic path."
Bruggeman introduced Silicon Realization as a way of going from a fragmented solution to a holistic design flow, based on three conditions -- a unified representation of intent, the efficient use of design abstraction, and convergence on the final goal of signoff.
From there, Chi-Ping Hsu, senior vice president of R&D for Silicon Realization, illustrated how Cadence is providing these capabilities in several key areas. He talked about recent progress within the Cadence Encounter, Virtuoso, Incisive, and Allegro platforms, and mentioned Silicon Realization "initiatives" in these areas:
- Low power design
- Gigagate-gigahertz design (in a reasonable period of time!)
- Verification, including the UVM methodology and emulation
- System-in-package (SiP) co-design
- Mixed-signal design and verification
Hsu left the details of mixed-signal design to Dave Desharnais, product marketing group director for Silicon Realization, who provided a hands-on look of some unique capabilities in the Cadence mixed-signal solution. With screenshots of schematics and layouts, he illustrated four key concepts:
- Analog behavioral modeling and its relationship to mixed-signal verification
- Modeling power intent in mixed-signal blocks
- Analog/digital interoperability - the connection between teams
- Bringing it all together with mixed-signal design closure
There were plenty of examples of intent, abstraction, and convergence in this demo. For example, analog behavioral modeling represented abstraction, mixed-signal IP included power intent, and convergence resulted in design closure following full-chip extraction and timing analysis. In one detailed example, Desharnais showed how a shielding constraint can be easily passed from the analog environment into digital placement and routing.
CDNLive! Silicon Valley included much more, including an inspiring user perspective from Raul "Ty" Garibay of Texas Instruments, and a panel on EDA360 with speakers from ARM, IBM, GLOBALFOUNDRIES, and Open-Silicon. These events will be subjects of upcoming blog posts.
CDNLive! On-Demand will be available at this location Nov. 3, and will include content from the General Session and the Technical Tracks. Access requires a Cadence.com account.
Photo by Joe Hupcey III