A session at last week's EDA Virtual Conference, sponsored by Open Systems Media, provided a good update on analog/mixed-signal design challenges as process nodes shrink. Speakers from Cadence and Magma Design Automation also talked about what's needed to solve those challenges.
The session was titled, "Analog and Mixed-Signal: Trends, Tips, Tools, and Thoughts." Presenters were Mladen Nizic, director of mixed-signal solutions marketing at Cadence, and Ashutosh Mauskar, vice president of marketing and business development at Magma. An archive of the one-hour session, along with the four other sessions at the virtual conference, is available as noted below. (The archive also includes a presentation by Steve Leibson of Cadence on "The Next Big Thing" in EDA, as noted in the EDA360 Insider blog).
We've often heard that "analog doesn't scale," but that wasn't the message here. Analog can scale to lower process nodes - but not without difficulty. Collaboration with foundries is key. "We at Cadence work closely with all major foundries to address challenges of advanced nodes to make analog design possible at 65nm, 45nm and beyond," Nizic said.
Mixed-Signal From an Analog Perspective
One thing I realized during this presentation is that I have had what you might call a "digital centric" view of mixed-signal design. That is, I mostly saw it as a challenge for digital SoC designers who are bringing analog blocks into their designs. But what about the analog designer who is coping with an influx of digital circuitry? Both presenters addressed that.
"Today there is almost no analog functionality not assisted by, or controlled by, some amount of digital," Nizic said. "It becomes quite a challenge to the analog designers who now have to cope with big blocks with a large amount of standard cell digital they have to design." Mauskar observed that "traditional" mixed-signal design was "big analog, small digital," but now mixed-signal is "digitally dominated with core analog automation."
Digital switching noise is, of course, a major problem for analog circuitry. This is why an early analysis of crosstalk and substrate noise is so important, Nizic said. And with the influx of digital, he noted, more low-power optimization techniques are required. Verifying low-power mixed-signal is a complicated task, and simulation alone may not be practical because of the large number of power modes. Thus, he said, formal methods of power verification are needed.
Here are some other challenges cited during the session:
- Both presenters talked about multi-objective or multi-dimensional design - that is, the need satisfy multiple demands such as functionality, performance, power, manufacturability, and yield.
- Lower process nodes bring more performance, but gains may be offset by the increasing impact of parasitics and variability.
- On a modern SoC, Nizic said, analog may occupy 50 percent of the area.
- Packaging often exceeds silicon costs and must be considered early.
- There is a constant need to improve mixed-signal simulation performance. Nizic noted the real number modeling (RNM) technology supported by Cadence, which approaches digital speeds.
- The block-based implementation methodology is running out of steam. Analog and digital designers must work much more closely together at advanced process nodes.
- While mixed-signal designs have grown more complicated, Mauskar said, analog design is still largely a manual process.
New Approach is Needed
Mauskar talked about bringing more automation to analog designers, and called for "model based" optimization and layout capabilities. Nizic talked about "seamlessly integrating" the interactive capabilities of the custom design environment with the automated capabilities of digital tools. He noted that Cadence accomplishes this by using the OpenAccess database to exchange design data and constraints.
"Today's mixed-signal design requires a much more tightly integrated solution with unified design intent that enables the management of design abstraction throughout the design cycle," Nizic said. "And it needs to be supported with engines that enable design convergence for multiple targets within time schedules and cost."
At the conclusion of the session, moderator Don Dingee of Embedded Computing Design asked about mixed-signal design challenges at 32nm and below. Nizic mentioned three: increasing variability, complexity, and constraint management. Mauskar pointed to a growing discrepancy between pre-layout and post-layout circuit performance.
Check out the archive if you want to hear more. To find the archive, click here and look for EDA Virtual Conference -- EDA: The Next Big Things. This is one conference you can "attend" from your desk when time permits.