Twenty-four is a big number when it comes to the number of one-hour webinars planned for a single two-month period. Yet that's what Cadence is planning in a new series of Silicon Realization webinars, slated to begin Oct. 20 and run through Dec. 10.
Over the past several months Cadence has offered a number of free webinars, many in co-operation with partners such as GLOBALFOUNDRIES, Imperas, and ARM. It's a great way to reach EDA users with targeted technical information, and nobody has to travel. I have attended, and blogged, about five of those previous webinars (see list at end of this post). All were of high quality with good, practical, technical information.
Quick reminder: Silicon Realization, as described in the EDA360 vision paper, includes everything it takes to get a complex design into silicon, including design, verification, and implementation. What sets it apart from "EDA" as we have so far known it is that Silicon Realization offers a deterministic, integrated flow with unified design intent, mixed abstraction levels, and design convergence.
Here's the list of topics for the upcoming webinars. All take place at 10:00 am Pacific time. You will find abstracts for each, and registration information, here. The webinars will be archived for later viewing, but you can only ask questions if you tune into the live event.
Whew! There's got to be something of interest here for almost every silicon designer. I hope to "see" you at some of these events.
DRC+ Now: Early DFM Signoff in the Custom Implementation Process - Oct. 20
DRC+ Now: Early DFM Signoff in the Digital Implementation Process - Oct. 21
Why Cadence Has the Best UVM Solution - Nov. 2
Metric-Driven Verification: The Galaxy Beyond Just Simulation - Nov. 9
Parasitic-Aware Design: A Complete Flow -Nov. 10
Maximizing Your Investment in the UVM - Nov. 11
Remote Enablement for a Globalized Workforce - Cadence and Open Text Enable Optimized Performance - Nov. 11
New Techniques for Debugging NonEQs and Aborts in Equivalence Checking - Nov. 15
Are You Losing Sleep Over How to Perform Top-Level Mixed-Signal SoC Verification? - Nov. 16
Analog Verification-How Do You Know Your Circuit is Right? Smart Verification! - Nov. 17
Design Techniques That Make ECOs Predictable - Nov. 18
Managing Parasitics in the Front End - Nov. 19
A Practical Guide to Exploiting Optimization in Custom Design Flows - Nov. 30
How to Eliminate Connectivity Bugs with Formal Verification - Nov. 30
Managing Parasitics in the Back End - Dec. 1
Achieve the Next Level of Verification Productivity with the Specman Advanced Option - Dec. 1
IC 6.1: A Leap Forward in Productivity - Dec. 2
Silicon Diagnostics - Enabling Greater Accuracy for Fast Silicon Evaluation -- Dec. 2
When IP Collides, Brace for Impact on Timing Constraints and CDC! Verify and Manage Your Timing Constraints and CDCs! - Dec. 3
Where Does Power Intent Come From? Create and Debug Power Intent for Low-Power Designs - Dec. 6
OpenPDK: What is the Goal of this Effort, and What is the Status? - Dec. 7
Migrating from VMM to the UVM - Dec. 8
Are You Ready for Your Next-Generation Analog/Mixed-Signal Product? - Dec. 9
Metric-Driven Synthesis: Collecting and Leveraging Inter and Intra Synthesis-Run Statistics to Improve Quality of Results - Dec. 10
Previous Industry Insights blogs about Cadence webinars:
Why Virtual Platforms Need Advanced Verification
Webinar: Some Practical Advice on Adopting ESL
3D-IC TSV Update: No Technology Roadblocks, But Cost Management is Needed
ARM, Cadence Webinar: How SOI Impacts Timing and Signal Integrity
OCV Webinar: Statistical Timing Finds a Niche