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Q&A: An Update on the Accellera UVM 1.0 Verification Standard

Comments(0)Filed under: Industry Insights, Accellera, OVM, verification, Verification IP, VIP, UVM, UVM 1.0, Krolikoski

The Universal Verification Methodology (UVM) is an emerging industry standard that will support verification IP (VIP) interoperability. Based largely on the existing Open Verification Methodology (OVM), it provides a class library and a methodology that facilitates test generation and simulation with SystemVerilog. In this interview Stan Krolikoski, Accellera board member and group director of standards at Cadence, comments on the delivery of UVM 1.0 in 2010 and the future of this standard.

Q: Stan, can you give us a quick history of UVM?

A: The Accellera Verification Intellectual Property Technical Subcommittee (VIP TSC) voted in December 2009 to adopt OVM, which was developed by Cadence and Mentor Graphics, as the basis for UVM.  After a lot of technical work in which we were heavily involved, UVM 1.0 Early Adopter (EA) was released in May 2010. 

Q: Given that OVM provides an open methodology, why is it important for verification teams to adopt UVM?

A: OVM was never a standard.  It provided a "standard" (that is, uniform and well documented) methodology, but not one that was "standardized" (adopted by an international standards organization).  The adoption of a standardized methodology like UVM that runs on all of the major simulators will go a long way towards enabling the true verification interoperability that has been the VIP TSC's goal.

Q: How does the UVM 1.0 Early Adopter release compare to OVM 2.1.1? Is UVM 1.0 EA production ready?

A: UVM 1.0 EA is almost identical to OVM 2.1.1, except for typographical changes (changing o's to u's) and the addition of a few features from VMM such as a "message catching" facility.  Since UVM 2.1.1 is being successfully used in projects in multiple companies around the world, this means that UVM 1.0 EA is similarly production ready.

Q: What is the status of UVM right now?

A: In March 2010 a "top 10" list of critical features to be included in the UVM 1.0 release was adopted by the VIP TSC.  The group is now driving to get these features added into the 1.0 release late in Q4 2010.

Q: Why is it important to complete the full UVM 1.0 release in 2010?

A: There is a pent up demand for a full UVM release.  In many companies, the tag "Early Adopter" is seen as being almost equivalent to "not ready for prime time."  This was not the intent of the TSC in using this tag- UVM 1.0 EA has the proven quality inherited from OVM 2.1.1 and was therefore designed to be an early, not inferior, release.  Nonetheless, some design team leaders hesitate to adopt something termed "Early Adopter."

Q: What are the key technical additions in UVM 1.0?

A: The major new features in UVM 1.0 will be a new run-time phasing definition, a register package, and a package that will provide support for a subset of the Open SystemC Initiative's TLM2 [transaction level modeling] standard.  Several additional smaller features will be included in the 1.0 release. 

The run-time phasing feature will allow UVM verification components to control aspects of the simulation cycle such as reset, configuration, execution, and shutdown.  The register package will provide a connection between the description of registers and the verification environment to allow control, randomization, and coverage and so forth.  TLM2 support will allow UVM verification components such as sequences to interact with SystemC models written using the OSCI TLM 2 standard. 

Q: What is Cadence doing to help Accellera accelerate UVM 1.0 in 2010?

A:  Not surprisingly, given Cadence's long history of verification leadership, and our role in developing OVM upon which UVM is based, we have been very active in the technical work of the VIP TSC.  Indeed, it is fair to say that we have been actively driving technology into each technical item within UVM 1.0. 

In particular, we are working to add customer-driven features from the Cadence register package to the register package that is being developed by the TSC. We have also supplied, and continue to supply, code for other UVM features, and we are supplying a reference example for the UVM including the new technology added into UVM 1.0.  Of course, we have also been quite active in testing UVM features.

Q: What's next for Accellera and UVM?

A:  Cadence would like to see UVM extended to provide support for other design/verification languages such as e and SystemC.  UVM is currently defined only in terms of SystemVerilog.  This is a very good start, but for UVM to fulfill its promise, it must be extended to add support for other languages as well as interoperability between UVM VIP developed in any of these languages.  When such support is added, then UVM will be considerably closer to being a true Universal Verification Methodology.

Of course, the direction of UVM will be decided by the full VIP TSC.  Cadence will, therefore, work with other VIP TSC members, most of whom also desire support for multiple languages, to help set that direction.  We will also be open to other extensions to UVM that users need to efficiently verify their designs.

Finally, we think that the upcoming SystemVerilog version of UVM should be allowed to undergo a period of adoption by users, and eventual improvement based on user feedback.

Q: What should users of OVM/VMM and custom methodologies do in the next few weeks?

A: First and foremost, user companies should join the VIP TSC and participate in its activities.  This will allow the users to have their voices heard when future directions of UVM are decided.  Users should also keep an eye out for the release of UVM 1.0 from Accellera in late 2010, and start planning for migration to UVM in early 2011.

Q: Finally, how can readers learn more about UVM 1.0?

Interested readers should consult the VIP TSC's page on Accellera.org , the UVMWorld website, and the book A Practical Guide to Adopting the Universal Verification Methodology (UVM) by Sharon Rosenberg and Kathleen Meade. They can also download and explore the UVM Reference Flow which provides a detailed example that applies UVM to a reference design.

Richard Goering

Recent Cadence Community blogs about UVM 1.0:

Adam Sherer: "We Want UVM 1.0! When Do We Want It? Now!"

Tom Anderson: A Quick Check on the Status of UVM 1.0




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