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CDNLive! Hot Topic – OVM-Based Verification for Analog and Mixed-Signal

Comments(0)Filed under: Industry Insights, Analog, OVM, verification, mixed signal, Simulation, CDNLive!, UVM, Analog Simulation

The Open Verification Methodology (OVM) has helped thousands of verification engineers build structured testbenches and run coverage in digital environments. Can the same advantages be leveraged to verify analog IP and mixed-signal SoCs? Yes, according to a paper planned for CDNLive! Silicon Valley Oct. 26.


Why apply OVM to the mixed-signal world, how, and what are the challenges? To get some background on the subject, I talked to two of the paper’s co-authors – Neyaz Khan, architect at Cadence, and Yaron Kashai, distinguished verification engineer at Cadence.

Analog Complexity Grows 

Yaron noted that analog IP today is complex and reconfigurable, with digital control and requirements for power management. The result is a very large state space. Engineers thus need to measure their progress and create stimulus in a structured way, and OVM helps achieve both goals.


OVM provides base class support for hierarchical sequences, thus allowing complex stimulus generation. Yaron noted that engineers can use OVM to inject analog sequences. They can then drop in checkers that look for particular waveforms, shapes, or voltage levels. It’s also possible to drive digital and analog testing with one testbench and one verification plan. These capabilities “provide a lot of value compared to the way analog is usually designed, which is by eyeballing stuff,” he said.


Analog coverage “metrics” can be provided in a variety of ways, Neyaz noted. For instance, if you run a frequency sweep on a circuit, you can look at the gain. If you use voltage scaling, you can look at what voltage level you’re running at any given time.

Adoption Challenges 

Applying an OVM-based methodology to analog/mixed-signal verification raises some challenges. One is the cultural difference between digital verification engineers and analog designers. Yaron noted that analog designers interactively run simulation by hand, and rarely run regressions, whereas digital verification engineers are strongly focused on regression testing.


“When advanced [digital] verification techniques came around, people needed education and training,” Neyaz noted. “What makes the problem a little harder here is the need for some cross-domain knowledge. The verification guy may need to understand something about the analog, and the analog person may need to understand a little about the testbench.”


OVM, as you probably know, will be succeeded by the Accellera Universal Verification Methodology (UVM) standard. Thus far UVM is maintaining backward compatibility with the OVM 2.1.1 release, and everything said in the CDNLive! OVM paper should apply to UVM. For an update on UVM 1.0, see Tom Anderson’s recent blog.

Case Study – It Can Be Done!

The CDNLive! paper, scheduled for the SoC Realization track at 4:15 pm Oct. 26, will present a case study that applied OVM to analog/mixed-signal verification. The abstract, now available on-line, says:

This paper is based on pioneering work done through a partnership between LSI Shanghai and Cadence. A prototype was developed to demonstrate the benefits of applying an OVM-based verification flow to the verification of a complex analog block that is part of a live project. The advantages of this flow and positive results will be highlighted. The presenter will share his experiences in: 1) Applying the OVM to the verification of complex analog IP blocks and 2) Applying digital-centric mixed-signal verification (DMSV)-based techniques to model analog IP and use it in an OVM-based verification environment.

While CDNLive! registration is currently closed, a wait list is available, and technical sessions will be available on a microsite after the conference.


Ricihard Goering



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