When a single company offers 11 out of 28 paper presentations on a given day at a conference, that's a heavy involvement. Add to that a fireside chat, a panel on applications-driven development, and a session on Silicon Realization with the ARM Cortex-A15, and you can see the depth of Cadence activity at the upcoming ARM Technology Conference (ARM Techcon) Nov. 9-11.
This swirl of activity follows a deepening ecosystem partnership with ARM, which was illustrated by two recent announcements:
- A collaboration with ARM to develop an optimized System Realization approach for ARM processors including tools, ARM processor and physical IP, services, and methodology from embedded Linux to GDSII. (For more, see my previous blog).
- An optimized implementation methodology for Silicon Realization of the new ARM Cortex-A15, stemming from a collaboration that began while the processor was still under development.
Located at the Santa Clara Convention Center, ARM Techcon includes a Chip Design conference Tuesday Nov. 9, and a System and Software Design conference Nov. 10-11. Except for the panel, the Cadence activities listed below take place Nov. 9.
11 Technical Papers
Cadence is offering the following technical papers Nov. 9. As you can see, the scope ranges from architecture to GDSII. These papers will be offered throughout the day. Schedules and abstracts are available at the ARM Techcon web site.
- Reliability Analysis for the Nanometer Era
- Performance/Accuracy Trade-offs Using TLM2 Standard Virtual Prototypes
- Best Practices in ARM-Based SoC Power Management
- Design for Reliability with Circuit Level Simulation
- AMBA Based Design, Synthesis, and Functional Verification from TLM through RTL
- Building Integration Optimized IP for SoC Designs
- DFM: Starting With the End in Mind and "In Design"
- Mixed Signal Assertion Based Verification
- Prevent Problems with Timing Constraints When IPs Combine
- Layout-Dependent Effect (LDE) Variability Design
- Verification Solutions for Digitally Calibrated Analog Design
Special Session on Cortex-A15 MPCore
In September ARM announced its Cortex-A15 MPCore processor, its most advanced processor for mobile, consumer and infrastructure applications. As noted above, Cadence worked closely with ARM to develop an optimized implementation methodology. In a Nov. 9 session at ARM Techcon at 10:30 a.m., two Cadence engineers and two ARM engineers will show how to implement the Cortex-A15 and A9 so as to attain Gigahertz performance while minimizing power consumption.
John Bruggeman, Cadence CMO, and Simon Segars, executive VP and general manager of ARM's Physical IP division, will participate in a fireside chat at 5:00 p.m. Nov. 9. They'll share their views on where the electronics industry is going and what's needed to support the next generation of innovative products and applications. The chat will be followed by a reception.
Panel Discussion on Application-Driven Design
The panel discussion is entitled "Are System Developers Ready for Applications to Drive and Define a New World Order?" It will be moderated by Ron Wilson of EE Times and held Thursday, Nov. 11, at 2:00 p.m. in the ARM theater.
This discussion will help systems developers find better ways to create, integrate, and optimize systems comprised of hardware and software. It will explore many aspects of System Realization, including hardware/software integration. Panelists include:
- Dave Rusling, Linaro CTO, ARM
- Peter Ryser, director for system integration and validation, Xilinx
- Michael (Mac) McNamara, VP and general manager, Cadence
- Ashok Mehta, senior manager, TSMC
- Vahid Ordoubadian, senior engineer, Broadcom
Conference registration is available through EE Times. A free Exhibits pass lets you attend keynotes, theater sessions and other events.